XR21B1422IL40-0A Datasheet, PDF (47/60 Pages) Exar Corporation – Enhanced 2-Ch Full-Speed USB UART

Bit
1:0
Default
Description
0
POWER_MODE
This field determines power mode as reported in the configuration descriptor.
00: Bus powered mode
01: Self powered mode
10: Self powered mode
11: Invalid
RELEASE_MAJOR (0x018) - Read/Write OTP
Bit
7:0
Default
0
Major Release
Description
RELEASE_MINOR (0x019) - Read/Write OTP
Bit
7:0
Default
0
Minor Release
Description
AUTO_FLUSH (0x01A) - Read/Write OTP
This register controls whether the FIFO buffers are flushed on open and/or close events.
Bit
7:5
4
3
2
1
0
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
RX_CLOSE
0: Do not automatically flush the RX FIFO
1: Automatically flush the RX FIFO when the COM port is closed
0
RX_OPEN
0: Do not automatically flush the RX FIFO
1: Automatically flush the RX FIFO when the COM port is opened
0
TX_CLOSE
0: Do not automatically flush the TX FIFO
1: Automatically flush the TX FIFO when the COM port is closed
0
TX_OPEN
0: Do not automatically flush the TX FIFO
1: Automatically flush the TX FIFO when the COM port is opened
0
Reserved
This bit is reserved and should be written as ’0’.
XR21B1422
© 2014 Exar Corporation
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exar.com/XR21B1422
Rev 1A