XR21B1422IL40-0A Datasheet, PDF (24/60 Pages) Exar Corporation – Enhanced 2-Ch Full-Speed USB UART

XR21B1422
XR21B1422 Register Descriptions
UART_ENABLE (0x000) - Read/Write
The UART transmitter and receiver must be disabled before writing to any other UART registers except for the GPIO_SET,
GPIO_CLEAR, TX_BREAK and ERROR_STATUS registers.
Bit
15:2
1
0
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
Enable UART RX
0: UART RX disabled
1: UART RX enabled
0
Enable UART TX
0: UART TX disabled
1: UART TX enabled
FLOW_CONTROL (0x006) - Read/Write
This register selects the flow control mode. This register should only be written to when the UART is disabled. Writing to the
FLOW_CONTROL register when the UART is enabled will result in undefined behavior.
Bit
15:4
3
2:0
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
UART Half-Duplex Mode
0: Normal (full-duplex) mode. The UART can transmit and receive data at the same time.
1: UART Half-Duplex Mode. In half-duplex mode, any data on the RX pin is ignored when the UART is transmitting data.
000
Mode
000: Mode 0. No flow control, no address matching.
001: Mode 1. HW flow control enabled. Auto RTS/CTS or DTR/DSR must be selected by GPIO_MODE.
010: Mode 2. SW flow control enabled.
011: Mode 3. Multidrop mode - RX only after address match, TX independent. (Typically used with GPIO_MODE 3).
100: Mode 4. Multidrop mode - RX/TX only after address match. (Typically used with GPIO_MODE 4).
101 to 111: Reserved
XON_CHAR (0x007) - Read/Write
The XON_CHAR stores the 5 through 8 bit XON character that is used for Automatic Software Flow control. In 9 bit mode,
only bits 7 through 0 are used, i.e. bit 8 is always a ’0.’ Alternately, this register holds the unicast address for multi-drop appli-
cations with address matching mode.
Bit
15:8
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
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