XR21B1422IL40-0A Datasheet, PDF (50/60 Pages) Exar Corporation – Enhanced 2-Ch Full-Speed USB UART

PIN_CFG_USB_STAT2 (0x020) - Read/Write OTP
Controls the configuration of the USB_STAT2 pin during suspend state
Bit
7:5
4:2
1:0
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
SEL
000: Assert logic ’0’ during SUSPEND or USB BUS_RESET else logic ’1’
001: Assert logic ’1’ during SUSPEND else logic ’0’
010: Assert logic ’1’ during LOW_PWR else logic ’0’
011: Assert logic ’1’ during USB BUS_RESET else logic ’0’
100: Assert logic ’0’ during SUSPEND or USB BUS_RESET else logic ’1’
101: Assert logic ’0’ during SUSPEND else logic ’1’
110: Assert logic ’0’ during LOW_PWR else logic ’1’
111: Assert logic ’0’ during USB BUS_RESET else logic ’1’
0
CTRL
00: Invalid, do not use
01: Output, open drain
10: Output, push-pull
11: Invalid, do not use
XR21B1422
PIN_CFG_CLK (0x024) - Read/Write OTP
This register configures the functionality of the GPIO6/CLK pin.
Bit
7
6
5:2
1:0
Default
Description
0
PULLUP_EN
This register bit is used to enable the internal pull-up resistor. This setting will be ignored if GPIO6/CLK is configured as an
output.
0: Do not enable internal pull-up
1: Enable internal pull-up if configured as an input
0
PULLDOWN_EN
This register bit is used to enable the internal pull-down resistor. This setting will be ignored if GPIO6/CLK is configured as an
output.
0: Do not enable internal pull-down
1: Enable internal pull-down if configured as an input (will not be enabled if Pull up is enabled)
0
RESERVED
These bits are reserved and should be written as ’0’.
0
CTRL
00: GPIO6/CLK is configured as a GPIO input
01: GPIO6/CLK is configured as a GPIO open drain output
10: GPIO6/CLK is configured as a GPIO push-pull output
11: GPIO6/CLK is configured as a push-pull CLK output
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