XR21B1422IL40-0A Datasheet, PDF (14/60 Pages) Exar Corporation – Enhanced 2-Ch Full-Speed USB UART

XR21B1422
5, 6, 7 or 8 bit mode
1^ST byte 7 6 5 4 3 2 1 0 5, 6, and 7 = ‘0’ in 5, 6, or 7 bit mode
2^ND byte x x x x O F B P
9 bit mode
P = Parity Error (=’0' if not enabled)
B = Break
F = Framing Error
O = Overrun Error
X = ‘0’
1^ST byte 7 6 5 4 3 2 1 0
2^ND byte x x x x O F B 8
B = Break
F = Framing Error
O = Overrun Error
X = ‘0’
Figure 5: Wide Mode Receive Data Format
Wide mode receive operation with 9-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of the received
data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received / checked. The remainder of
the 2nd byte consists of the framing and overrun error bits and break status.
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags are historical
flags indicating that an error has occurred since the previous request. Therefore, no conclusion can be drawn as to which
specific byte(s) may have contained an actual error.
RX FIFO Low Latency
In normal operation all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to minimize host pro-
cessing. When there are 64 bytes of data in the RX FIFO, the XR21B1422 will acknowledge a bulk-in request from the host
and transfer the data packet. If there are less than 64 bytes in the RX FIFO, the XR21B1422 may respond to the bulk-in
request with a NAK indicating that data is not ready to transfer at that time. However, if there are less than 64 bytes in the
RX FIFO and no data has been received for more than 3 character times, the XR21B1422 will acknowledge the bulk-in
request and transfer any data in the RX FIFO to the USB host.
In some cases, especially when the baud rate is low, this behavior may increase latency unacceptably. The XR21B1422
has a low latency register bit that will enable the XR21B1422 to immediately transfer any received data in the RX FIFO to
the USB host without waiting for 3 character times. The custom driver may be used to automatically set the RX_FI-
FO_LOW_LATENCY register to enable low latency mode, or the user may manually set it. With the CDC-ACM driver, the
low latency mode is automatically set whenever the baud rate is set to a value of less than 40960 bps using the CDC_AC-
M_IF_SET_LINE_CODING command.
GPIO
Each UART has 10 GPIO pins in addition to the TX and RX pins. Each GPIO pin may also be configured for one or more
special functions. All GPIO pins as well as USB_STAT1 and USB_STAT2 may be configured for a variety of pin type options
using the GPIO_MODE register or by writing the OTP using XR_SET_OTP. All enabled pull-up and pull-down resistors are
maintained during the USB suspend state. Pin configurations set using XR_SET_OTP are enabled following the next
© 2014 Exar Corporation
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Rev 1A