XR21B1422IL40-0A Datasheet, PDF (17/60 Pages) Exar Corporation – Enhanced 2-Ch Full-Speed USB UART

XR21B1422
Multidrop mode with address matching
The XR21B1422 device has two address matching modes which are set by the FLOW_CONTROL and GPIO_MODE regis-
ters. These modes are intended for use in a multi-drop network application. Address matching may be used with any size
data character, as well as with and without parity. An address match occurs when the last (most significant) received data
bit or the parity bit, if there is one, is a ’1’ and the address matches the value stored in either the XON_CHAR or
XOFF_CHAR register. To send an address byte use 5, 6, 7, 8 or 9 bit data with either the most significant data bit a ’1’ or if
parity is used, set mark parity. To send data bytes, the most significant data bit must be a ’0’ or use space parity.
Receiver
If an address match occurs in either of the address matching modes, the address byte and all subsequent data bytes will be
loaded into the RX FIFO. The UART Receiver will automatically be disabled when an address byte is received that does not
match the values in the XON_CHAR or XOFF_CHAR characters.
Transmitter
In flow control mode 3, the UART transmitter will transmit irrespective of the RX address match. In flow control mode 4, the
UART will only transmit following an RX address match.
Programmable Turn-Around Delay
By default, the selected RS-485 half-duplex enable pin (either GPIO7/RS485 or GPIO5/RTS#/RS485) will be de-asserted
immediately after the stop bit of the last byte has been shifted. However, this may not be ideal for systems where the signal
needs to propagate over long cables. Therefore, the de-assertion of the RS-485 half-duplex enable can be delayed from 1
to 15 bit times via the XCVR_EN_DELAY register to allow for the data to reach distant UARTs.
UART Half-Duplex Mode
In UART half-duplex mode, the UART will ignore any data on the RX input when the UART is transmitting data. The half-
duplex mode can be configured using the FLOW_CONTROL register.
IR Mode
The XR21B1422 supports IR mode at a maximum baud rate of 2.5 Mbaud with transmit pulses of 3/16th or 4/16th of a bit
period and centered in the bit period. Receive data may be inverted to conform to some manufacturer’s non-standard
devices. IR mode is disabled by default but may be enabled by the IR_MODE register.
USB_STAT Pins
The XR21B1422 has two USB_STAT output pins that may be used to indicate 3 different statuses in either positive or nega-
tive polarity. The SUSPEND status indicates that the XR21B1422 device has been placed into a suspended state by the
USB host. This output can then be used by external circuitry, for example, to power down devices in order to meet USB
requirements for suspend mode. The LOW_POWER status is similar to the SUSPEND status, but LOW_POWER is also
asserted for high power devices (any device that consumes more than 100 mA of VBUS power from the USB host), before
the device is configured during enumeration by the USB host. For low power devices (devices that consume 100 mA or less
of VBUS power), SUSPEND and LOW_POWER status outputs are functionally the same. Lastly, the BUS_RESET output
status is asserted any time the XR21B1422 device is being reset by the USB host. This status output could be used, for
example, by an FPGA or other logic device to synchronize this external logic with the XR21B1422 device.
Suspend Mode Settings
The USE_SUSPEND bit controls the GPIO pins when the XR21B1422 device is suspended by the USB host. If USE_SUS-
PEND is cleared to ’0,’ the GPIO pins retain their output states when the device is suspended. When USE_SUSPEND is
set to ’1’, the GPIO pin’s behavior is defined by the SUSPEND_STATE and SUSPEND_MODE registers, with the following
exceptions: GPIO0/CLK when configured as an output clock will always be driven low, i.e the clock output will stop, and
GPIO1/RTS#/RS485 or GPIO3/RS485 when configured as auto. RS-485 half-duplex enable will always be de-asserted.
© 2014 Exar Corporation
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exar.com/XR21B1422
Rev 1A