XR21B1422IL40-0A Datasheet, PDF (45/60 Pages) Exar Corporation – Enhanced 2-Ch Full-Speed USB UART

CDC_ACM_GPIO_INT_MASK_MSB (0x00E) - Read/Write OTP
Bit
7:3
2
1:0
Default
Description
0
0
0x100
Reserved
These bits are reserved and should be written as ‘0’.
GPIO Interrupt Mask of RX
0: A change in the input pin's state causes the device to generate an interrupt packet
1: A change in the input pin's state does not cause the device to generate an interrupt packet
GPIO Interrupt Mask of GPIO[9:0]
0: A change in the input pin's state causes the device to generate an interrupt packet
1: A change in the input pin's state does not cause the device to generate an interrupt packet
XR21B1422
CDC_ACM_BAUD_THRES_0 (0x00F) - Read/Write OTP
Bit
7:0
Default
Description
0
CDC_ACM_BAUD_THRES[7:0]
Least significant byte of the CDC_ACM baud rate threshold override for low latency mode.
CDC_ACM_BAUD_THRES_1 (0x010) - Read/Write OTP
Bit
7:0
Default
Description
0
CDC_ACM_BAUD_THRES[15:8]
Second least significant byte of the CDC_ACM baud rate threshold override for low latency mode.
CDC_ACM_BAUD_THRES_2 (0x011) - Read/Write OTP
Bit
7:0
Default
Description
0
CDC_ACM_BAUD_THRES[23:16]
Most significant byte of the CDC_ACM baud rate threshold override for low latency mode.
VID_LSB (0x012) - Read/Write OTP
Bit
7:0
Default
0
Vendor ID[7:0]
Least significant byte of the Vendor ID.
Description
© 2014 Exar Corporation
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exar.com/XR21B1422
Rev 1A