XRT79L72 Datasheet, PDF (36/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L72
REV. P1.0.2
PRELIMINARY
xr
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PIN #
D15
A14
NAME
RxUClav/RxPPA
RxUClkO/
RxPClkO
TYPE
O
O
DESCRIPTION
Receive UTOPIA - Cell Available/Receive POS-PHY Interface - Packet
Available:
The function of this output pin depends upon whether the XRT79L72 has been
configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode - RxUClav - Receive UTOPIA Interface - Cell Available Indi-
cator Output:
The Receive UTOPIA Interface block will assert this output pin in order to indi-
cate that the RxFIFO has some ATM cell data that needs to be read out by the
ATM Layer Processor. This signal will be asserted (e.g., toggles to a logic
"HIGH" level) if the RxFIFO contains at least one full ATM cell of data. This sig-
nal toggle "low" if the RxFIFO is depleted of data, or if it contains less than one
full cell of data. The exact behavior of the RxUClav output pin, as a function of
"UTOPIA Level" is presented below.
Multi-PHY Operation - UTOPIA Level 2:
When the XRT79L72 device is operating in a Multi-PHY Application and is con-
figured to operate in the UTOPIA Level 2 Mode, then this signal will be tri-stated
until the RxUClk cycle following the assertion of a valid address on the Receive
UTOPIA Address bus input pins (e.g., if the contents on the Receive UTOPIA
Address bus pins , RxUAddr[4:0], match that which have been assigned to this
particular Receive UTOPIA Interface block). Afterwards, this output pin will be
driven either "high" or "low" depending upon the current fill status of the
RxFIFO.
Multi-PHY Operation - UTOPIA Level 3:
When the XRT79L72 device is operating in a Multi-PHY Application, then this
signal will be tri-stated until two RxUClk cycles following the assertion of a valid
address on the Receive UTOPIA Address bus input pins (e.g., if the contents of
the Receive UTOPIA Address bus input pins, RxUAddr[4:0], match that which
have been assigned to this particular Receive UTOPIA Interface block). After-
wards, this output pin will be driven either "high" or "low" depending upon the
current fill status of the RxFIFO.PPP Mode - RxPPA - Receive POS-PHY Inter-
face - Packet Available Indicator OutputThe XRT79L72 device will drive this
output pin "high" whenever a (programmable) number of bytes of incoming PPP
Packet data are available to be read from the RxFIFO by the Link Layer Proces-
sor. The exact behavior of the RxPPA output pin, as a function of "POS-PHY
Level" is presented below.
POS-PHY Level 2:
When the XRT79L72 device is configured to operate in the POS-PHY Level 2
Mode, then this signal will be tri-stated until the RxPClk cycle following the
assertion of a valid address on the Receive POS-PHY Address bus input pins
(e.g., if the contents on the Receive POS-PHY Address bus pins, RxPAddr[4:0],
match that which have been assigned to this particular Receive POS-PHY Inter-
face block). Afterwards, this output pin will be driven either "high" or "low"
depending upon the current fill status of the RxFIFO.
POS-PHY Level 3:
When the XRT79L72 device is configured to operate in the POS-PHY Level 3
Mode, then this signal will be tri-stated until two RxPClk cycles following the
assertion of a valid address on the Receive POS-PHY Address bus input pins
(e.g., if the contents on the Receive POS-PHY Address bus pins, RxPAddr[4:0],
match that which have been assigned to this particular Receive POS-PHY Inter-
face block). Afterwards, this output pin will be driven either "high" or "low"
depending upon the current fill status of the RxFIFO.
Receive UTOPIA Interface Clock/Receive POS-PHY Interface Clock Out-
put:
This clock output signal is derived from an internal PLL.
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