XRT79L72 Datasheet, PDF (29/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L72
REV. P1.0.2
PIN #
M5
J23
NAME
RxLCD_0/
RxOutClk_0/
RxHDLCDat0_7
RxLCD_1/
RxOutClk_1/
RxHDLCDat1_7
TYPE
O
O
DESCRIPTION
Receive Loss of Cell Delineation indicator/Receive Output Clock signal/
Receive HDLC Controller Data Bus - Bit 7 Output:
The function of these output pins depend upon whether the XRT79L72 has
been configured to operate in the ATM, Clear-Channel Framer or High Speed
HDLC Controller Mode.
ATM Mode - RxLCD (Loss of Cell Delineation Defect Indicator)
The XRT79L72 device will assert this output pin (e.g., toggle it "high") anytime
(and for the duration that) the Receive ATM Cell Processor block is declaring
the LCD (Loss of Cell Delineation) defect condition. The XRT79L72 device will
negate this output pin (e.g., toggle it "low") whenever the Receive ATM Cell Pro-
cessor block is not currently declaring the LCD defect condition.
J2
RxLOS_0
E25
RxLOS_1
E2
RxPRED_0
D22
RxPRED_1
Clear-Channel Framer Mode - RxOutClk:
These clock signals function as the Transmit Payload Data Input Interface clock
source, if the XRT79L72 has been configured to operate in the loop-timing
mode.
In this mode, the local terminal equipment is expected to input data to the TxSer
input pins, upon the rising edge of these clock signals. The XRT79L72 will use
the rising edge of these signals to sample the data on the TxSer inputs.
High-Speed HDLC Controller Mode - RxHDLCDat_7:
These output pins along with RxHDLCDatn_[6:0] functions as the Receive
HDLC Controller byte wide output data bus. These particular output pins func-
tion as the MSB (Most Significant Bit) of the Receive HDLC Controller byte wide
data bus. The Receive HDLC Controller will output the contents of all HDLC
frames via this output data bus, upon the rising edge of the RxHDLCClk output
signals. Hence, the user's local terminal equipment should be designed/config-
ured to sample this data upon the falling edge of the RxHDLCClk output clock
signals.
O Framer/UNI - Loss of Signal Output Indicator:
O These pins are asserted when the Receive Section of the XRT79L72 encoun-
ters 180 consecutive 0's (for DS3 applications) or 32 consecutive 0's (for E3
applications) via the RxPOS and RxNEG pins. These pins will be negated once
the Receive DS3/E3 Framer has detected at least 60 "1s" out of 180 consecu-
tive bits (for DS3 applications) or has detected at least four consecutive 32 bit
strings of data that contain at least 8 "1s" in the receive path.
O Receiver Red Alarm Indicator - Receive PLCP Processor:
O _{• The XRT79L72 device will assert this output pin (e.g., toggle it "high")}
anytime (and for the duration that) the Receive PLCP Processor block is
currently declaring any of the following defect conditions. PLCP OOF - Out of
Frame Defect Condition
• PLCP LOF - Loss of Frame Defect Condition
Conversely, the XRT79L72 device will negate this output pin (e.g., tog-
gle it "low") anytime (and for the duration that) the Receive PLCP Pro-
cessor block is NOT declaring any of the above-mentioned defect con-
ditions.
NOTE: These output pins are only valid if the XRT79L72 has been configured to
operate in the ATM/PLCP Mode.
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