XRT79L72 Datasheet, PDF (30/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L72
REV. P1.0.2
PIN #
F1
E22
NAME
RxPOOF_0
RxPOOF_1
E3
RxPLOF_0
E21
RxPLOF_1
J4
RxOHEnable_0/
RxHDLCDat0_5
F26 RxOHEnable_1/
RxHDLCDat1_5
J3
RxOH_0/
RxHDLCDat0_6
E26
RxOH_1/
RxHDLCDat1_6
PRELIMINARY
xr
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
O
O
O
O
O
O
O
O
DESCRIPTION
Receive PLCP Processor Block - PLCP Out of Frame Defect Indicator:
The XRT79L72 device will assert this output pin (e.g., toggle it "high") anytime
(and for the duration that) the Receive PLCP Processor block is currently
declaring the PLCP OOF (Out of Frame) defect condition.
Conversely, the XRT79L72 device will negate this output pin (e.g., toggle it
"low") anytime (and for the duration that) the Receive PLCP Processor block is
NOT declaring the PLCP OOF defect condition.
NOTE: These output pins are only active if the XRT79L72 has been configured
to operate in both the UNI and PLCP Mode.
Receive PLCP Processor Block - PLCP Loss of Frame Defect Indicator
Output
The XRT79L72 device will assert this output pin (e.g., toggle it "high")
anytime (and for the duration that) the Receive PLCP Processor block
is currently declaring the PLCP LOF (Loss of Frame) defect condi-
tion.Conversely, the XRT79L72 device will negate this output pin (e.g.,
toggle it "low") anytime (and for the duration that) the Receive PLCP
Processor block is NOT declaring the PLCP LOF defect condition.
NOTE: These output pins are only active is the XRT79L72 has been configured
to operate in the ATM/PLCP Mode.
Receive Overhead Data Output Interface - Enable Output/Receive HDLC
Controller Data Bus - Bit 5 output:
The function of these output pins depend upon whether the XRT79L72 has
been configured to operate in the Clear-Channel Framer Mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOHEnable:
The XRT79L72 will assert these output signals for one RxOHClk period when it
is safe for the local terminal equipment to sample the data on the RxOH output
pins.
High-Speed HDLC Controller Mode - RxHDLCDat_5:
These output pins along with RxHDLCDatn_[4:0], RxHDLCDatn_6 and
RxHDLCDatn_7 functions as the Receive HDLC Controller byte wide output
data bus. The Receive HDLC Controller will output the contents of all HDLC
frames via this output data bus, upon the rising edge of the RxHDLCClk output
signals. Hence, the user's local terminal equipment should be designed/config-
ured to sample this data upon the falling edge of the RxHDLCClk output clock
signals.
Receive Overhead Data Output Interface - output/Receive HDLC Controller
Data Bus - Bit 6 output:
The function of these output pins depend upon whether the XRT79L72 has
been configured to operate in the Clear-Channel Framer mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOH:
All overhead bits, which are received via the Receive Section of the XRT79L72
will be output via these output pins, upon the rising edge of RxOHClk.
High-Speed HDLC Controller Mode - RxHDLCDat_6:
These output pins along with RxHDLCDatn_[5:0] and RxHDLCDatn_7 functions
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via this output data bus,
upon the rising edge of the RxHDLCClk output signals. Hence, the user's local
terminal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signals.
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