XRT79L72 Datasheet, PDF (26/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L72
REV. P1.0.2
PIN #
A11
NAME
TxMod
C3
TxUData_0/
TxPData_0
B2
TxUData_1/
TxPData_1
A1
TxUData_2/
TxPData_2
A2
TxUData_3/
TxPData_3
B3
TxUData_4/
TxPData_4
A3
TxUData_5/
TxPData_5
D5
TxUData_6/
TxPData_6
C4
TxUData_7/
TxPData_7
B4
TxUData_8/
TxPData_8
A4
TxUData_9/
TxPData_9
C5
TxUData_10/
TxPData_10
B5
TxUData_11/
TxPData_11
A5
TxUData_12/
TxPData_12
C6
TxUData_13/
TxPData_13
B6
TxUData_14/
TxPData_14
A6
TxUData_15/
TxPData_15
PRELIMINARY
xr
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
DESCRIPTION
I Transmit PPP Data Bus - Modulo Indicator:
This input pin is used to specify the number of valid packet octets are being
placed on the TxPData[15:0] input pins.
The Link Layer Processor is expected to set this input pin "Low" when both bytes
on the TxPData[15:0] data bus is valid packet data. Conversely, the Link Layer
Processor is expected to set this input pin "High" when only the upper octet has
valid packet data.
NOTES:
1. This input pin is only active if the XRT79L72 has been configured to
operate in the PPP Mode.
2. The Link Layer Processor is expected to set this input pin to the appro-
priate state, as each 16-bit word is being written into the TxPData[15:0]
data bus.
I Transmit UTOPIA Data Bus Inputs/Transmit POS-PHY Data Bus Inputs:
The function of these input pins depends upon whether the XRT79L72 is operat-
ing in the ATM UNI Mode or in the PPP Mode.
ATM UNI Operation - TxUData[15:0]:
These input pins comprise the Transmit UTOPIA Data Bus input pins. When the
ATM Layer Processor wishes to transmit ATM cell data through the XRT72L72
ATM UNI, it must place this data on these pins. The data, on the Transmit UTO-
PIA Data Bus is latched into the Transmit UTOPIA Interface block upon the rising
edge of TxUClk.
PPP Operation - TxPDATA[15:0]
These input pins comprise the Transmit POS-PHY Data Bus input pins. When a
Network Processor wishes to transmit PPP data through the XRT79L72 Framer/
UNI IC, it must place this data on these pins. The data, on the Transmit POS-
PHY Data Bus is latched into the Transmit POS-PHY Interface block upon the
rising edge of TxPClk.
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