XRT79L72 Datasheet, PDF (17/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

xr
PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L72
REV. P1.0.2
PIN #
E5
C21
AA1
V22
NAME
TxGFCClk_0
TxGFCClk_1
TxNib0_3/
TxPOHIns_0/
TxHDLCDat0_3
TxNib1_3/
TxPOHIns_1/
TxHDLCDat1_3
TYPE
DESCRIPTION
O Transmit GFC Nibble-Field Serial Input port - Clock Output signal:
O These signals, along with TxGFC and TxGFCMSB combine to function as the
Transmit GFC Nibble-field serial input port. These output signals function as the
demand clock signal for this port. The user will specify the value of the GFC
field, within a given ATM cell, by serially transmitting its four bit-value into the
TxGFC input pins. The Transmit GFC Nibble-Field serial input port will latch the
contents of TxGFC upon the rising edge of these clock signals. Hence, the local
terminal equipment should be designed to place its outbound GFC bits on to the
TxGFC line, upon the falling edge of these clock signals.
NOTE: These output pins are only active if the XRT79L72 has been configure to
operate in the ATM Mode.
I Transmit Nibble Interface - Bit 3/Transmit PLCP Path Overhead Insert
enable/Transmit HDLC Controller Data Bus - Bit 3 input:
The function of these input pins depend upon whether the XRT79L72 is config-
I
ured to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Con-
troller Mode or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_3:
If the XRT79L72 is configured to operate in the Nibble-Parallel Mode, then these
input pins will function as the bit 3 (MSB) input to the Transmit Nibble-Parallel
input interface. The Transmit Payload Data Input Interface block will sample
these signals (along with TxNib_0 through TxNib_2) upon the falling edge of
TxNibClk.
NOTE: These input pins are inactive if the XRT79L72 is configured to operate in
the Serial Mode.
ATM/PLCP Mode - TxPOHIns:
f the XRT79L72 is configured to operate in the ATM Mode, and if (within the ATM
Mode, the chip is also configured to operate in the PLCP Mode), then these input
pins function as the Transmit PLCP Path Overhead Port - Enable input pin. In
this mode, the user can externally insert desired path overhead byte values into
the outbound PLCP frames.
The Transmit PLCP Path Overhead Input port becomes active whenever the
user asserts these input pins by pulling them "High". Once this occurs, the data,
residing upon the TxPOH input pins will be sampled upon the rising edge of the
TxPOHClk signals.
These input pins are inactive if the XRT79L72 is configured to operate in the
Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_3:
If the XRT79L72 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 3 within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
14