XRT79L72 Datasheet, PDF (27/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L72
REV. P1.0.2
PIN #
NAME
TYPE
RECEIVE SYSTEM SIDE INTERFACE PINS
DESCRIPTION
M2
RxAIS_0/
RxNib0_2/
RxHDLCDat0_2
H23
RxAIS_1/
RxNib1_2/
RxHDLCDat1_2
O Receive AIS Pattern Indicator/Receive Nibble Output Interface - Bit 2/
Receive HDLC Controller Data Bus - Bit 2 output pin:
The function of these output pins depend upon whether the XRT79L72 has
O ^{been configured to operate in the Clear-Channel Framer/Nibble-Parallel Inter-}
face Mode, the High-Speed HDLC Controller Mode, or in the other modes.
Other Modes - RxAIS:
These output pins are driven "High" whenever the Receive Section of the
XRT79L72 has detected and is currently declaring an AIS (Alarm Indicator Sig-
nal) condition.
Clear-Channel Framer/Nibble-Parallel Interface Mode - RxNib_2:
If the XRT79L72 is configured to operate in the Nibble-Parallel Mode, then
these output pins will function as the bit 2 output from the Receive Nibble-Paral-
lel output interface. The Receive Payload Data Output Interface block will out-
put these signals (along with RxNibn_0, RxNibn_1, and RxNibn_3) upon the
rising edge of the RxClk output signals.
High-Speed HDLC Controller Mode - RxHDLCDat_2:
These output pins along with RxHDLCDatn_[7:3] and RxHDLCDatn_[1:0] func-
tions as the Receive HDLC Controller byte wide output data bus. The Receive
HDLC Controller will output the contents of all HDLC frames via this output data
bus, upon the rising edge of the RxHDLCClk output signals. Hence, the user's
local terminal equipment should be designed/configured to sample this data
upon the falling edge of the RxHDLCClk output clock signals.
M1
RxRED_0/
RxNib0_3/
RxHDLCDat0_3
H24
RxRED_1/
RxNib1_3/
RxHDLCDat1_3
O Receive Section Red Alarm Indicator/Receive Nibble Interface Output pin -
Bit 3/Receive HDLC Controller Data Bus output pin - Bit 3:
The function of this output pin depends upon whether the XRT79L72 has been
O ^{configured to operate in the Clear-Channel Framer/Nibble-Parallel Mode, the}
High-Speed HDLC Controller Mode, or in some other mode.
Clear-Channel Framer/Nibble-Parallel Mode - RxNib_3:
The XRT79L72 will output Received data from the remote terminal equipment
to the local terminal equipment via this pin, along with RxNib_0 through
RxNib_2. This particular output pin functions as the LSB. The data at this pin is
updated on the rising edge of the RxClk output signal. Hence, the user's local
terminal equipment should sample this signal upon the falling edge of RxClk.
High-Speed HDLC Controller Mode - RxHDLCDat_3:
This output pin along with RxHDLCDat_[7:4] and RxHDLCDat_[2:0] functions
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via this output data bus,
upon the rising edge of the RxHDLCClk output signal. Hence, the user's local
terminal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signal.
Other Modes - RxRED - RED Alarm/Defect Indicator Output pin:
The XRT79L72 device will assert this output pin (e.g., toggle it "high") in
order to indicate that the Receive DS3/E3 Framer block is currently de-
claring at least one of the following defect conditions.
• LOS - Loss of Signal Defect Condition
• OOF - Out of Frame Defect Condition
• AIS - Alarm Indication Signal Defect Condition.
The XRT79L72 device will negate this output pin (e.g., toggle it "low")
anytime that the Receive DS3/E3 Framer block is NOT currently declar-
ing any of the above-mentioned defect conditions.
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