XRT79L72 Datasheet, PDF (19/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L72
REV. P1.0.2
PIN #
AA3
V24
AB1
V25
NAME
TxNib0_1/
Tx8KREF_0/
TxHDLCDat0_1
TxNib1_1/
Tx8KREF_1/
TxHDLCDat1_1
TxNib0_0/
TxGFC1_0
TxHDLCDat0_0
TxNib1_0/
TxGFC_1/
TxHDLCDat1_0
TYPE
DESCRIPTION
I Transmit Nibble Input Interface - Bit 1/Transmit PLCP Framing 8kHz Refer-
ence Input/Transmit HDLC Controller Data Bus - Bit 1 Input:
The function of these input pins depend upon whether the XRT79L72 is config-
I
ured to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Con-
troller Mode, or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_1:
If the XRT79L72 is configured to operate in the Nibble-Parallel Mode, then these
input pins will function as the bit 1 input to the Transmit Nibble-Parallel input
interface. The Transmit Payload Data Input Interface block will sample this sig-
nals (along with TxNibn_0, TxNibn_2 and TxNibn_3) upon the falling edge of
TxNibClk.
NOTE: These input pins are inactive if the XRT79L72 is configured to operate in
the Serial Mode.
ATM/PLCP Mode - Tx8KREF:
If the XRT79L72 is configured to operate in the ATM/PLCP Mode, then the
Transmit PLCP Processor can be configured to synchronize its PLCP frame gen-
eration to these input clock signals. The Transmit PLCP Processor will also use
these input signals to compute the nibble-trailer stuff opportunities.
NOTE: These input pins are inactive if the use has configured the XRT79L72 to
operate in the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_1:
If the XRT79L72 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 1 within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
I Transmit Nibble Interface - Bit 0/Transmit GFC Input pin/Transmit HDLC
Controller Data Bus - Bit 0 Input:
The function of these input pins depend upon whether the XRT79L72 is config-
I
ured to operate in the Clear-Channel Framer Mode, the High Speed HDLC Con-
troller Mode or in the ATM Mode.
Clear-Channel Framer Mode - TxNib_0:
If the XRT79L72 is configured to operate in the Nibble-Parallel Mode, then these
input pins will function as the bit 0 (LSB) input to the Transmit Nibble-Parallel
input interface. The Transmit Payload Data Input Interface block will sample
these signals (along with TxNibn_1 through TxNibn_3) upon the falling edge of
TxNibClk.
NOTE: These input pins are inactive if the XRT79L72 is configured to operate in
the Serial Mode.
ATM Mode - TxGFC:
These signals, along with TxGFCMSB, and TxGFCClk combine to function as
the Transmit GFC Nibble Field serial input port. The user will specify the value of
the GFC field, within a given ATM cell, by serially transmitting its four bit-value
into these input pins. Each of these four bits will be clocked into the port upon
the rising edge of the TxGFCClk output signals.
High-Speed HDLC Controller Mode - TxHDLCDat_0:
If the XRT79L72 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 0 (the LSB) within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
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