XRT79L72 Datasheet, PDF (28/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L72
REV. P1.0.2
PIN #
M3
H22
NAME
RxOOF_0/
RxNib0_1/
RxHDLCDat0_1
RxOOF_1/
RxNib1_1/
RxHDLCDat1_1
M4
RxNib0_0/
RxHDLCDat0_0
J22
RxNib1_0/
RxHDLCDat1_0
PRELIMINARY
xr
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TYPE
O
O
O
O
DESCRIPTION
Receive Out of Frame Indicator/Receive Nibble Interface Output pin - Bit 1/
Receive HDLC Controller Data Bus Output pin - Bit 1:
The function of these output pins depend upon whether the XRT79L72 has
been configured to operate in the Clear-Channel Framer/Nibble-Parallel Mode
or the High-Speed HDLC Controller Mode.
Clear-Channel Framer/Nibble-Parallel Mode - RxNib_1:
The XRT79L72 will output Received data from the remote terminal equipment
to the local terminal equipment via these pins, along with RxNibn_0, RxNibn_2
and RxNibn_3: These particular output pins function as the LSB. The data at
these pins are updated on the rising edge of the RxClk output signals. Hence,
the user's local terminal equipment should sample these signals upon the falling
edge of RxClk.
High-Speed HDLC Controller Mode - RxHDLCDat_1:
These output pins along with RxHDLCDatn_[7:2] and RxHDLCDatn_0 functions
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via these output data bus,
upon the rising edge of the RxHDLCClk output signals. Hence, the user's local
terminal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signals.
All other Modes - RxOOF:
The UNI Receive DS3 Framer will assert these output signals whenever it has
declared an Out of Frame (OOF) condition with the incoming DS3 frames.
These signals are negated when the framer correctly locates the F- and M-bits
and regains synchronization with the DS3 frame.
Receive Nibble Interface Output pin - Bit 0/Receive HDLC Controller Data
Bus output pin - Bit 0:
The function of these output pins depend upon whether the XRT79L72 has
been configured to operate in the Clear-Channel/Nibble-Parallel Mode, the
High-Speed HDLC Controller Mode, or in some other mode.
Clear-Channel/Nibble-Parallel Mode - RxNib_0:
The XRT79L72 will output Received data from the remote terminal equipment
to the local terminal equipment via these pins, along with RxNibn_1 through
RxNibn_3. These particular output pins function as the LSB.
The data at these pins are updated on the rising edge of the RxClk output sig-
nals. Hence, the user's local terminal equipment should sample these signals
upon the falling edge of RxClk.
High-Speed HDLC Controller Mode - RxHDLCDat_0:
These output pins along with RxHDLCDatn_[7:1] function as the Receive HDLC
Controller byte wide output data bus. These particular output pins function as
the LSB (Least Significant Bit) of the Receive HDLC Controller byte wide data
bus. The Receive HDLC Controller will output the contents of all HDLC frames
via this output data bus, upon the rising edge of the RxHDLCClk output signals.
Hence, the user's local terminal equipment should be designed/configured to
sample this data upon the falling edge of the RxHDLCClk output clock signals.
NOTE: These output pins are only active if the XRT79L72 is configured to oper-
ate in the Clear-Channel/Nibble-Parallel Mode or in the High-Speed HDLC Con-
troller Mode. These outputs are inactive for all remaining modes.
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