XRT79L72 Datasheet, PDF(25/72 Page) Exar Corporation – 2

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XRT79L72 Datasheet, PDF (25/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY

2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L72

REV. P1.0.2

PIN #

NAME

TxUAddr_0

TxUAddr_1

TxUAddr_2

TxUAddr_3

TxUAddr_4

TYPE

DESCRIPTION

I Transmit UTOPIA Address Bus/Transmit POS-PHY Address Bus:

The exact function of these input pins depends upon whether the XRT79L72

device has been configured to operate in the ATM UNI or PPP Modes.

ATM UNI Mode -TxUAddr[4:0] - Transmit UTOPIA Address Bus:

These input pins comprise the Transmit UTOPIA Address Bus input pins. The

Transmit UTOPIA Address Bus is only in use when the XRT79L72 is operating in

the Multi-PHY mode. Whenever the ATM Layer processor wishes to poll or write

data to a particular UNI (PHY-Layer) device, it will provide the address of the "tar-

get UNI" on the Transmit UTOPIA Address Bus. The contents of the Transmit

UTOPIA Address Bus input pins are sampled on the rising edge of TxUClk clock

signal. The Transmit UTOPIA Interface block will compare the data on the

Transmit UTOPIA Address Bus with the pre-programmed UTOPIA Address

value (which was loaded into the XRT79L72 device by writing the appropriate

data into both the "Transmit UTOPIA Port Address" Register (Address = 0x0593)

and the "Transmit UTOPIA Port Number" Register (Address = 0x0597). If these

two values are identical and the TxUENB* input pin is asserted, then the TxU-

Clav output pin will be driven to the appropriate state (based upon the TxFIFO fill

level) for the Cell Level handshake mode of operation. If these two values do not

match, then the Transmit UTOPIA Interface block will continue to tri-state the

"TxUClav" output pin.

NOTE: These input pins are only active if the XRT79L72 device has been

designed into a "Multi-PHY" Application. If the user intends to design the

XRT79L72 into a "Single-PHY" Application, then he/she should tie these input

pins to GND.

PPP Mode - TxPAddr[4:0] - Transmit POS-PHY Interface Address Bus Input

Pins:

These input pins comprise the Transmit POS-PHY Address Bus input pins.

Whenever the Link Layer Processor wishes to poll or write data to a particular

PHY-Layer device, it will provide the address of the "target PHY-Layer device" on

the Transmit POS-PHY Address Bus. The contents of the Transmit POS-PHY

Address Bus input pins are sampled on the rising edge of TxPClk. The

XRT79L72 device will compare the data on the Transmit POS-PHY Address Bus

with the pre-programmed POS-PHY Address value (which was loaded into the

XRT79L72 device by writing the appropriate data into the "Transmit POS-PHY

Interface - Transmit Control Register - Byte 0" (Address = 0x0582). If these two

values are identical and the "TxPENB*" input pin is asserted, then the TxPPA

output pin will be driven to the appropriate state (based upon the TxFIFO fill

level). If these two values do not match, then the Transmit POS-PHY Interface

block will continue to tri-state the "TxPPA" output pin.

NOTE: These input pins are only active if the XRT79L72 device has been config-

ured to operate in either the ATM UNI or PPP Modes. The user should tie these

input pins to GND if he/she wishes to operate the XRT79L72 device in either the

"Clear-Channel Framer" or "High-Speed HDLC Controller" Modes.

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