XRT79L72 Datasheet, PDF (31/72 Pages) Exar Corporation – 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L72
REV. P1.0.2
PIN #
J5
F25
K1
F24
N3
J26
NAME
RxOHClk_0/
RxHDLCClk_0
RxOHClk_1/
RxHDLCClk_1
RxOHFrame_0/
RxHDLCDat0_4
RxOHFrame_1/
RxHDLCDat1_4
RxFrame_0
RxFrame_1
TYPE
O
O
O
O
0
O
DESCRIPTION
Receive Overhead Data Output Interface - clock/Receive HDLC Controller
- Clock output:
The function of these output pins depend upon whether the XRT79L72 has
been configured to operate in the Clear-Channel Framer mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOHClk:
The XRT79L72 will output the overhead bits within the incoming DS3 or E3
frames via the RxOH output pins, upon the falling edge of these clock signals.
As a consequence, the user's local terminal equipment should use the rising
edge of these clock signals to sample the data on both the RxOH and RxO-
HFrame output pins.
NOTE: These clock signals are always active.
High-Speed HDLC Controller Mode - RxHDLCClk:
These output pins function as the Receive HDLC Controller Data bus clock out-
put. The Receive HDLC Controller block outputs the contents of all received
HDLC frames via the Receive HDLC Controller Data bus (RxHDLCDatn_[7:0])
upon the rising edge of these clock signals. Hence, the user's local terminal
equipment should be designed/configured to sample these data upon the falling
edge of these clock signals.
Receive Overhead Data Interface - Framing Pulse indicator/Receive HDLC
Controller Data Bus - Bit 4 output:
The function of these output pins depend upon whether the XRT79L72 has
been configured to operate in the Clear-Channel Framer Mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOHFrame:
These output pins pulse "High" whenever the Receive Overhead Data Output
Interface block outputs the first overhead bit of a new DS3 or E3 frame.
High-Speed HDLC Controller Mode - RxHDLCDat_4:
These output pins along with RxHDLCDatn_[3:0] and RxHDLCDatn_[7:5] func-
tions as the Receive HDLC Controller byte wide output data bus. The Receive
HDLC Controller will output the contents of all HDLC frames via this output data
bus, upon the rising edge of the RxHDLCClk output signals. Hence, the user's
local terminal equipment should be designed/configured to sample this data
upon the falling edge of the RxHDLCClk output clock signals.
Receive Boundary of DS3 or E3 Frame Output indicator:
The function of these output pins depend upon whether or not the XRT79L72 is
operating in the Clear-Channel Framer/Nibble-Parallel Mode.
Clear-Channel Framer/Nibble-Parallel Mode:
The Receive Section of the XRT79L72 will pulse these output pins "High" for
one nibble period, when the Receive Payload Data Output interface block is
driving the very first nibble of a given DS3 or E3 frame, on the RxNibn[3:0] out-
put pins.
Clear-Channel Framer/Serial Mode:
The Receive Section of the XRT79L72 will pulse these output pins "High" for
one bit period, when the Receive Payload Data Output interface block is driving
the very first bit of a given DS3 or E3 frame, on the RxSer output pin.
All Other Modes:
The Receive Section of the XRT79L72 will pulse these output pins "High" when
the Receive DS3/E3 Framer block is processing the first bit within a new DS3 or
E3 frame.
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