XR16C850 Datasheet, PDF (36/55 Pages) Exar Corporation – UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

XR16C850
ENHANCED MODE SELECT REGISTER (EMSR)
This register is accessible only when FCTR Bit-6 is set
to “1”.
EMSR BIT-0: “Write only”
0 = Receive FIFO count register. The scratch pad
register is used to provide the receive FIFO count when
it is read.
1 = Transmit FIFO count register. The scratch pad
register is used to provide the transmit FIFO count when
it is read.
EMSR BIT-1: “Write only”
0 = Normal.
1 = Alternate receive - transmit FIFO count. When
EMSR Bit-0=1 and EMSR Bit-1=1, scratch pad register
is used to provide the receive - transmit FIFO count
when it is read every alternate read cycle. The TRG Bit-
7 will provide FIFO count mode information, TRG Bit-
7=0 receive mode, TRG Bit-7=1 transmit mode.
EMSR BIT-2: “Write only”
This bit selects and enables the DMA interface function
on the 52-pin device, –DACK, -DRQ and TC become
active. Only TX or RX DMA can be enabled at one time.
0 = Enable RX DMA
1 = Enable TX DMA
EMSR BIT 3-7:
Reserved for future use.
XR16C850 EXTERNAL RESET CONDITIONS
REGISTERS RESET STATE
IER
ISR
LCR, MCR
LSR
MSR
FCR, EFR
FCTR
EMSR
SCPAD
IER BITS 0-7 = logic 0
ISR BIT-0=1, ISR BITS 1-7 = logic
0
BITS 0-7 = logic 0
LSR BITS 0-4 = logic 0,
LSR BITS 5-6 = logic 1 LSR, BIT 7
= logic 0
MSR BITS 0-3 = logic 0,
MSR BITS 4-7 = logic levels of the
input signals
BITS 0-7 = logic 0
BITS 0-7 = logic 0
BITS 0-7 = logic 0
BITS 0-7 = logic 1
SIGNALS
TX
-OP1
-OP2
-RTS
-DTR
-RXRDY
-TXRDY
IRQn/INT
RESET STATE
Logic 1
Logic 1
Logic 1
Logic 1
Logic 1
Logic 1 (STD mode),/ Three state
(PC mode)
Logic 0 (STD mode) / Three state
(PC mode)
Logic 0 (STD mode) / Three state
(PC mode)
Rev. 1.20
36