XR16C850 Datasheet, PDF (17/55 Pages) Exar Corporation – UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

XR16C850
Internal Registers
The 850 provides 15 internal registers for monitoring and
control. These registers are shown in Table 3 below.
Twelve registers are similar to those already available in
the standard 16C550. These registers function as data
holding registers (THR/RHR), interrupt status and con-
trol registers (IER/ISR), a FIFO control register (FCR),
line status and control registers, (LCR/LSR), modem
status and control registers (MCR/MSR), program-
mable data rate (clock) control registers (DLL/DLM),
and a user assessable scratchpad register (SPR).
Beyond the general 16C550 features and capabilities,
the 850 offers an enhanced feature register set called
EFR, Xon/Xoff 1-2, TRG, FCTR, and EMSR. Register
functions are more fully described in the following
paragraphs.
A2 A1 A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Receive Holding Register
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Scratchpad Register
Baud Rate Register Set (DLL/DLM): Note *3
0
0
0
0
0
1
LSB of Divisor Latch
MSB of Divisor Latch
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Register Set (Xon/off 1-2, TRG, FCTR, EFR, EMSR): Note *4
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
FIFO Trigger Register
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
FIFO trigger counter
Feature Control Register
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
Enhanced Mode Select Register
Table 3. INTERNAL REGISTERS
Note *3: These registers are accessible only when LCR bit-7 is set to a logic 1.
Note *4: Enhanced Feature Registers are accessible only when the LCR is set to “BF” hex.
Rev. 1.20
17