XR16C850 Datasheet, PDF (18/55 Pages) Exar Corporation – UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

XR16C850
FIFO Operation
The 128 byte transmit and receive data FIFO’s are
enabled by the FIFO Control Register (FCR) bit-0. With
16C550 devices, the user can only set the receive
trigger level but not the transmit trigger level. The 850
provides independent trigger levels for both receiver and
transmitter. To remain compatible with 16C550, the
transmit interrupt trigger level is set to 16 following a
reset. It should be noted that the user can set the
transmit trigger levels by writing to the FCR register, but
activation will not take place until EFR bit-4 is set to a
logic 1. The receiver FIFO section includes a time-out
function to ensure data is delivered to the CPU. An
interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading
of a character or the receive trigger level has not been
reached. (see hardware flow control for a description of
this timing).
Hardware Flow Control
When automatic hardware flow control is enabled, the
850 monitors the -CTS pin for a remote buffer overflow
indication and controls the -RTS pin for local buffer
overflows. Automatic hardware flow control is selected
by setting bits 6 (RTS) and 7 (CTS) of the EFR register
to a logic 1. If -CTS transitions from a logic 0 to a logic
1 indicating a flow control request, ISR bit-5 will be set
to a logic 1 (if enabled via IER bit 6-7), and the 850 will
suspend TX transmissions as soon as the stop bit of the
character in process is shifted out. Transmission is
resumed after the -CTS input returns to a logic 0,
indicating more data may be sent.
The 850 has a new feature that provides flow control
trigger hysteresis while maintains compatibility to
16C650A and 16C550. With the Auto RTS function
enabled, an interrupt is generated when the receive
FIFO reaches the programmed RX trigger level. The -
RTS pin will not be forced to a logic 1 (RTS Off), until the
receive FIFO reaches the upper limit of the hysteresis
level. The -RTS pin will return to a logic 0 after the RX
data buffer (FIFO) is unloaded to the lower limit of the
hysteresis level. Under the above described conditions
the 850 will continue to accept data until the receive
FIFO gets full. The Auto RTS function is initiated when
the –RTS output pin is asserted to logic 0 (RTS On).
Below shows the 650A and 850 hysteresis level of “N”
with respect to Auto RTS flow control levels.
FCTR
Trigger
Bit-1 and 0 Level
Selection (characters)
RTS
Hysteresis
(characters)
INT
Pin
Activation at
00
8
8
00
16
16
00
24
24
00
28
28
01
N
+/-4
N
10
N
+/-6
N
10
N
+/-6
N
-RTS
De-asserted
(characters)
-RTS
Asserted
(characters)
16
24
28
28
N plus 4
N plus 6
N plus 6
0
8
16
24
N minus 4
N minus 6
N minus 6
Rev. 1.20
18