XR16C850 Datasheet, PDF (29/55 Pages) Exar Corporation – UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

XR16C850
TRIGGER TABLE-A (Receive)
“Default setting after reset, ST16C550 mode”
BIT-7 BIT-6
FIFO trigger level
0
0
1
0
1
4
1
0
8
1
1
14
interrupt status register is read, the interrupt status is
cleared. However it should be noted that only the current
pending interrupt is cleared by the read. A lower level
interrupt may be seen after re-reading the interrupt
status bits. The Interrupt Source Table 6 (below) shows
the data values (bit 0-5) for the six prioritized interrupt
levels and the interrupt sources associated with each of
these interrupt levels.
TRIGGER TABLE-B (Receive)
BIT-7 BIT-6
FIFO trigger level
0
0
8
0
1
16
1
0
24
1
1
28
TRIGGER TABLE-C (Receive)
BIT-7 BIT-6
FIFO trigger level
0
0
8
0
1
16
1
0
56
1
1
60
TRIGGER TABLE-D (Receive)
BIT-7 BIT-6
FIFO trigger level
X
X
User programmable
Trigger levels
Interrupt Status Register (ISR)
The 850 provides six levels of prioritized interrupts to
minimize external software interaction. The Interrupt
Status Register (ISR) provides the user with six interrupt
status bits. Performing a read cycle on the ISR will
provide the user with the highest pending interrupt level
to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the
Rev. 1.20
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