XR16C850 Datasheet, PDF (24/55 Pages) Exar Corporation – UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

XR16C850
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the fifteen 850 internal registers. The assigned bit
functions are more fully defined in the following paragraphs.
XR16C850 ACCESSIBLE REGISTERS
A2 A1 A0
Register
[Default]
Note *3
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
General Registers are accessible when LCR bit-7 is not a Logic 1 or "BF" Hex
0 0 0 RHR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
000
THR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
001
IER [00]
0/
-CTS
interrupt
0/
-RTS
interrupt
0/
Xoff
interrupt
0/
Sleep
mode
modem
status
interrupt
receive
line
status
interrupt
transmit
holding
register
receive
holding
register
010
FCR [00]
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
0/TX
trigger
(MSB)
0/TX
trigger
(LSB)
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
010
ISR [01]
0/
FIFO’s
enabled
0/
FIFO’s
enabled
0/
-RTS,
-CTS
0/
Xoff
int
priority
bit-2
int
priority
bit-1
int
priority
bit-0
int
status
011
LCR [00]
divisor
latch
enable
set
break
set
parity
even
parity
parity
enable
stop
bits
word
length
bit-1
word
length
bit-0
100
MCR [00]
Clock
0/
0/
select
IRRT
Xon
enable
Any
loop
back
-OP2
-OP1
-RTS
-DTR
101
LSR [60]
0/
FIFO
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
110
MSR [00]
-CD
-RI
-DSR
-CTS
delta
delta
delta
delta
-CD
-RI
-DSR
-CTS
1 1 1 SCPAD [FF]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
Baud rate generator registers are accessible only when LCR bit-7 is set to Logic 1.
0 0 0 DLL [00]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0 0 1 DLM [00]
bit-15 bit-14 bit-13 bit-12 bit-11 bit-10
bit-9
bit-8
Rev. 1.20
24