XR16C850 Datasheet, PDF (34/55 Pages) Exar Corporation – UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

XR16C850
Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/ Xoff1.
Receiver compares Xon1 and Xon2,
Xoff1 and Xoff2
0
1
1
1
Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
0
1
1
No transmit flow control
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Table 7. SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-4:
Enhanced function control bit. The content of the IER
bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7
are enabled when this bit is set to logic 1. After
modifying these bits EFR bit-4 can be set to a logic 0 to
latch the new values. This feature prevents existing
software from altering or overwriting the 850 enhanced
functions.
Logic 0 = disable/latch enhanced features. IER bits 4-
7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are saved
to retain the user settings, then IER bits 4-7, ISR bits 4-
5, FCR bits 4-5, and MCR bits 5-7 are initialized to the
default values shown in the Internal Register Table. After
a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with
ST16C550 mode. (normal default condition).
Logic 1 = Enables the enhanced functions. When this
bit is set to a logic 1 all enhanced features of the 850 are
enabled and user settings stored during a reset will be
restored.
EFR BIT-5:
Logic 0 = Special Character Detect Disabled (normal
default condition)
Logic 1 = Special Character Detect Enabled. The 850
compares each incoming receive character with Xoff-2
data. If a match exists, the received data will be
transferred to FIFO and ISR bit-4 will be set to indicate
detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character.
When this feature is enabled, the normal software flow
control must be disabled (EFR bits 0-3 must be set to
a logic 0).
EFR BIT-6:
Automatic RTS is used for hardware flow control by
enabling EFR bit-6. The user must assert –RTS to
initiate this function. When AUTO RTS is selected, an
interrupt will be generated when the receive FIFO is filled
to the programmed Rx trigger level and -RTS will go to
a logic 1 when it reaches the upper limit of the hysterisis
level. -RTS will return to a logic 0 when data is unloaded
to the lower limit of the hysterisis. The state of this
register bit changes with the status of the hardware flow
control. -RTS functions normally when hardware flow
control is disabled.
0 = Automatic RTS flow control is disabled. (normal
default condition)
1 = Enable Automatic RTS flow control.
Rev. 1.20
34