XR16C850 Datasheet, PDF (19/55 Pages) Exar Corporation – UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

XR16C850
Software Flow Control
When software flow control is enabled, the 850 com-
pares one or two sequential receive data characters with
the programmed Xon or Xoff-1,2 character value(s). If
receive character(s) (RX) match the programmed val-
ues, the 850 will halt transmission (TX) as soon as the
current character(s) has completed transmission.
When a match occurs, the receive ready (if enabled via
Xoff IER bit-5) flags will be set and the interrupt output
pin (if receive interrupt is enabled) will be activated.
Following a suspension due to a match of the Xoff
characters values, the 850 will monitor the receive data
stream for a match to the Xon-1,2 character value(s). If
a match is found, the 850 will resume operation and
clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow
control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/
Xoff characters and suspend/resume transmissions.
When double 8-bit Xon/Xoff characters are selected, the
850 compares two consecutive receive characters with
two software flow control 8-bit values (Xon1, Xon2, Xoff1,
Xoff2) and controls TX transmissions accordingly. Un-
der the above described flow control mechanisms, flow
control characters are not placed (stacked) in the user
accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow
control needs to be executed, the 850 automatically
sends an Xoff message (when enabled) via the serial TX
output to the remote modem. The 850 sends the Xoff-1,2
characters as soon as received data passes the pro-
grammed trigger level. To clear this condition, the 850
will transmit the programmed Xon-1,2 characters as
soon as receive data drops below the programmed
trigger level.
Special Feature Software Flow Control
A special feature is provided to detect an 8-bit character
when bit-5 is set in the Enhanced Feature Register
(EFR). When this character is detected, it will be placed
on the user accessible data stack along with normal
incoming RX data. This condition is selected in conjunc-
tion with EFR bits 0-3. Note that software flow control
should be turned off when using this special mode by
setting EFR bit 0-3 to a logic 0.
The 850 compares each incoming receive character
with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to
indicate detection of special character (see Figure 9).
Although the Internal Register Table shows each X-
Register with eight bits of character information, the
actual number of bits is dependent on the programmed
word length. Line Control Register (LCR) bits 0-1 defines
the number of character bits, i.e., either 5 bits, 6 bits, 7
bits, or 8 bits. The word length selected by LCR bits 0-
1 also determines the number of bits that will be used
for the special character comparison. Bit-0 in the X-
registers corresponds with the LSB bit for the receive
character.
Time-out Interrupts
Three special interrupts have been added to monitor the
hardware and software flow control. The interrupts are
enabled by IER bits 5-7. Care must be taken when
handling these interrupts. Following a reset the trans-
mitter interrupt is enabled, the 850 will issue an interrupt
to indicate that transmit holding register is empty. This
interrupt must be serviced prior to continuing opera-
tions. The LSR register provides the current singular
highest priority interrupt only. It could be noted that CTS
and RTS interrupts have lowest interrupt priority. A
condition can exist where a higher priority interrupt may
mask the lower priority CTS/RTS interrupt(s). Only after
servicing the higher pending interrupt will the lower
priority CTS/ RTS interrupt(s) be reflected in the status
register. Servicing the interrupt without investigating
further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it
is important to service these interrupts correctly. Re-
ceive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER bit-0). The
receiver issues an interrupt after the number of charac-
ters have reached the programmed trigger level. In this
case the 850 FIFO may hold more characters than the
programmed trigger level. Following the removal of a
data byte, the user should recheck LSR bit-0 for
additional characters. A Receive Time Out will not occur
if the receive FIFO is empty. The time out counter is
reset at the center of each stop bit received or each time
the receive holding register (RHR) is read. The actual
time out value is T (Time out length in bits) = 4 X P
Rev. 1.20
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