XR16C850 Datasheet, PDF (35/55 Pages) Exar Corporation – UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

XR16C850
EFR bit-7:
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled.
(normal default condition)
Logic 1 = Enable Automatic CTS flow control. Transmis-
sion will stop when -CTS goes to a logical 1. Transmis-
sion will resume when the -CTS pin returns to a logical
0.
FEATURE CONTROL REGISTER (FCTR)
This register controls the XR16C850 new functions that
are not available on ST16C550 or ST16C650A.
FCTR BIT 0-1:
User selectable -RTS delay timer for hardware flow
control application. After reset, these bits are set to “0”
to select the next trigger level for hardware flow control.
FCTR FCTR
Bit-1 Bit-0
0
0
0
1
1
0
1
1
Trigger
level
Next trigger level
4 char+trigger level
6 char+trigger level
8 char+trigger level
FCTR BIT-2:
0 = Select RX input as encoded IrDa data.
1 = Select RX input as active high encoded IrDa data.
FCTR BIT-3:
Auto RS-485 Direction control.
0 = Standard ST16C550 mode. Transmitter generates
an interrupt when transmit holding register becomes
empty and transmit shift register is shifting data out.
1 = Enable Auto RS485 Direction Control function. The
direction control signal, -OP1 pin, changes its output
logic state from low to high one bit time after the last stop
bit of the last character is shifted out. Also, the Transmit
interrupt generation is delayed until the transmitter shift
register becomes empty. The -OP1 output pin will
automatically return to logic high state when a data byte
is loaded into the TX FIFO.
FCTR BIT 4-5:
Transmit / receive trigger table select.
FCTR
Bit-5
0
0
1
1
FCTR
Bit-4
0
1
0
1
Table
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
FCTR BIT-6:
Register mode select.
0 = Scratch Pad register is selected as general read and
write register. ST16C550 compatible mode.
1 = FIFO count register, Enhanced Mode Select Reg-
ister. Number of characters in transmit or receive
holding register can be read via scratch pad register
when this bit is set. Enhanced Mode is selected when
it is written into it.
FCTR BIT-7:
Programmable trigger register select.
0 = Receiver programmable trigger level register is
selected.
1 = Transmitter programmable trigger level register is
selected.
TRIGGER LEVEL / FIFO DATA COUNT REGISTER
(TRG)
User programmable transmit / receive trigger level
register.
TRG BIT 0-7: Write only.
these bits are used to program desired trigger levels that
are not available in standard tables.
TRG BIT 0-7: Read only.
Transmit / receive FIFO count. Number of characters in
transmit or receive FIFO can be read via this register.
Rev. 1.20
35