RFM95 Datasheet, PDF (92/121 Pages) List of Unclassifed Manufacturers – Low Power Long Range Transceiver Module

WIRELESS & SENSING
RFM95/96/97/98(W)
PRELIMINARY
DATASHEET
Name
(Address)
Bits
7-5
4
3
2
RegAfcFei
(0x1a)
1
0
RegAfcMsb
(0x1b)
7-0
RegAfcLsb
(0x1c)
7-0
RegFeiMsb
(0x1d)
7-0
RegFeiLsb
(0x1e)
7-0
7
RegPreambleDetect
(0x1f)
6-5
4-0
RegRxTimeout1
(0x20)
7-0
RegRxTimeout2
(0x21)
7-0
RegRxTimeout3
(0x22)
7-0
RegRxDelay
(0x23)
7-0
Variable Name
unused
AgcStart
reserved
unused
AfcClear
AfcAutoClearOn
AfcValue(15:8)
AfcValue(7:0)
FeiValue(15:8)
FeiValue(7:0)
PreambleDetectorOn
PreambleDetectorSize
PreambleDetectorTol
TimeoutRxRssi
TimeoutRxPreamble
TimeoutSignalSync
InterPacketRxDelay
Mode
Default
value
FSK/OOK Description
r
- unused
wt 0x00 Triggers an AGC sequence when set to 1.
rw 0x00 reserved
-
- unused
wc 0x00 Clear AFC register set in Rx mode. Always reads 0.
Only valid if AfcAutoOn is set
0 Æ AFC register is not cleared at the beginning of the automatic
rw 0x00 AFC phase
1 Æ AFC register is cleared at the beginning of the automatic
AFC phase
rw
0x00
MSB of the AfcValue, 2’s complement format. Can be used to
overwrite the current AFC value
rw
0x00
LSB of the AfcValue, 2’s complement format. Can be used to
overwrite the current AFC value
rw
-
MSB of the measured frequency offset, 2’s complement. Must be
read before RegFeiLsb.
rw
-
LSB of the measured frequency offset, 2’s complement
Frequency error = FeiValue x Fstep
Enables Preamble detector when set to 1. The AGC settings
rw
0x01 supersede this bit during the startup / AGC phase.
* 0 Æ Turned off
1 Æ Turned on
rw
0x01
*
Number of Preamble bytes to detect to trigger an interrupt
00 Æ 1 byte
10 Æ 3 bytes
01 Æ 2 bytes
11 Æ Reserved
rw
0x0A Number or chip errors tolerated over PreambleDetectorSize.
* 4 chips per bit.
Timeout interrupt is generated TimeoutRxRssi*16*T_bit after
rw 0x00 ^{switching to Rx mode if Rssi interrupt doesn’t occur (i.e.}
RssiValue > RssiThreshold)
0x00: TimeoutRxRssi is disabled
Timeout interrupt is generated TimeoutRxPreamble*16*T_bit after
rw 0x00 switching to Rx mode if Preamble interrupt doesn’t occur
0x00: TimeoutRxPreamble is disabled
Timeout interrupt is generated TimeoutSignalSync*16*T_bit after
rw 0x00 the Rx mode is programmed, if SyncAddress doesn’t occur
0x00: TimeoutSignalSync is disabled
rw
0x00
Additional delay before an automatic receiver restart is launched:
Delay = InterPacketRxDelay*4*Tbit
RC Oscillator registers
Page 92
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