RFM95 Datasheet, PDF (30/121 Pages) List of Unclassifed Manufacturers – Low Power Long Range Transceiver Module

RFM95/96/97/98(W)
Principle of Operation
Thanks to its dual port configuration, it is possible to simultaneously store both transmit and receive information in the FIFO
data buffer. The register FifoTxBaseAddr specifies the point in memory where the transmit information is stored. Similarly,
for receiver operation, the register FifoRxBaseAddr indicates the point in the data buffer where information will be written to
in event of a receive operation.
By default, the device is configured at power-up so that half of the available memory is dedicated to Rx (FifoRxBaseAddr
initialized at address 0x00) and the other half is dedicated for Tx (FifoTxBaseAddr initialized at address 0x80).
However, due to the contiguous nature of the FIFO data buffer, the base addresses for Tx and Rx are fully configurable
across the 256 byte memory area. Each pointer can be set independently anywhere within the FIFO. To exploit the
maximum FIFO data buffer size in transmit or receive mode, the whole FIFO data buffer can be used in each mode by
setting the base addresses FifoTxBaseAddr and FifoRxBaseAddr at the bottom of the memory (0x00).
The FIFO data buffer is cleared when the device is put in SLEEP mode, consequently no access to the FIFO data buffer is
possible in sleep mode. However, the data in the FIFO data buffer are retained when switching across the other LoRa
modes of operation, so that a received packet can be retransmitted with minimum data handling on the controller side. The
FIFO data buffer is not self-clearing (unless if the device is put in sleep mode) and the data will only be “erased” when a
new set of data is written into the occupied memory location.
The actual location to be read from, or written to, over the SPI interface is defined by the address pointer FifoAddrPtr.
Before any read or write operation it is hence necessary to initialise this pointer to the corresponding base value. Upon
reading or writing to the FIFO data buffer (RegFifo) the address pointer will then increment automatically.
The register FifoRxBytesNb defines the size of the memory location to be written in the event of a successful receive
operation. On the other hand PayloadLength indicates the size of the memory location to be transmitted. In implicit header
mode, the FifoRxBytesNb is not used as the number of payload bytes is known. Otherwise, in explicit header mode, the
initial size of the receive buffer is set to the packet length in the received header. The variable FifoRxCurrentAddr indicates
the location of the last packet received in the FIFO so that the last packet received can be easily read by pointing the
FifoAddrPtr to this register.
It is important to notice that all the received data will be written to the FIFO data buffer even if the CRC is invalid. This
allows for post-processing of received data for debug purposes for instance. It is also imporant to note that when receiving,
if the packet size exceeds the buffer memory allocated for the Rx it will overwrite the transmit portion of the data buffer.
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