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RFM95 Datasheet, PDF (104/121 Pages) List of Unclassifed Manufacturers – Low Power Long Range Transceiver Module
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WIRELESS & SENSING
RFM95/96/97/98(W)
PRELIMINARY
DATASHEET
Name
(Address)
Bits
Variable Name
Mode Reset
LoRaTM Description
RegLna
(0x0C)
7-5 LnaGain
4-3 LnaBoostLf
2 reserved
LNA gain setting:
000 Æ not used
001 Æ G1 = maximum gain
010 Æ G2
rwx 0x01 011 Æ G3
100 Æ G4
101 Æ G5
110 Æ G6 = minimum gain
111 Æ not used
Low Frequency (RFI_LF) LNA current adjustment
rw 0x00 00 Æ Default LNA current
Other Æ Reserved
rw 0x00 reserved
1-0 LnaBoostHf
RegFifoAddrPtr
7-0
(0x0D)
RegFifoTxBaseAd
dr
7-0
(0x0E)
RegFifoRxBaseAd
dr
7-0
(0x0F)
RegFifoRxCurrent
Addr
7-0
(0x10)
FifoAddrPtr
FifoTxBaseAddr
FifoRxBaseAddr
FifoRxCurrentAddr
7
RxTimeoutMask
6
RxDoneMask
5
PayloadCrcErrorMask
4
RegIrqFlagsMask
(0x11)
3
ValidHeaderMask
TxDoneMask
2
CadDoneMask
1
FhssChangeChannelM
ask
0
CadDetectedMask
High Frequency (RFI_HF) LNA current adjustment
rw 0x00 00 Æ Default LNA current
11 Æ Boost on, 150% LNA current
Lora page registers
rw 0x00 SPI interface address pointer in FIFO data buffer.
rw 0x80 write base address in FIFO data buffer for TX modulator
rw 0x00 read base address in FIFO data buffer for RX demodulator
r
n/a Start address (in data buffer) of last packet received
rw
0x00
Timeout interrupt mask: setting this bit masks the corresponding
IRQ in RegIrqFlags
rw
0x00
Packet reception complete interrupt mask: setting this bit masks
the corresponding IRQ in RegIrqFlags
rw
0x00
Payload CRC error interrupt mask: setting this bit masks the
corresponding IRQ in RegIrqFlags
rw
0x00
Valid header received in Rx mask: setting this bit masks the
corresponding IRQ in RegIrqFlags
rw
0x00
FIFO Payload transmission complete interrupt mask: setting this
bit masks the corresponding IRQ in RegIrqFlags
rw
0x00
CAD complete interrupt mask: setting this bit masks the
corresponding IRQ in RegIrqFlags
rw
0x00
FHSS change channel interrupt mask: setting this bit masks the
corresponding IRQ in RegIrqFlags
rw
0x00
Cad Detected Interrupt Mask: setting this bit masks the
corresponding IRQ in RegIrqFlags
Page 104
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