RF64 Datasheet, PDF (67/76 Pages) List of Unclassifed Manufacturers – ADVANCED COMMUNICATIONS & SENSING

ADVANCED COMMUNICATIONS & SENSING
7.3.1. Optimized Receive Cycle
The lowest-power Rx cycle is the following:
RF64
IDD
IDDR
3.0mA typ.
RF64
IDDFS
1.3mA typ.
IDDST
65uA typ.
IDDSL
100nA typ.
Rx
time
Wait
TS RE
RF64 can be put in
Any other mode
Receiver is ready :
-RSSI sampling is valid after a 1/Fdev period
-Received data is valid
Wait
TS OS
Wait
TS FS
Set RF64 in Rx mode
Wait for Receiver settling
Set RF64 in FS mode
Wait for PLL settling
Set RF64 in Standby mode
Wait for XO settling
Time
Figure 49: Optimized Rx Cycle
Note: If the lock detect indicator is available on an external interrupt pin of the companion uC, it can be used to
optimize TS_FS, without having to wait the maximum specified TS_FS.
Page 67 of 76
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