RF64 Datasheet, PDF (3/76 Pages) List of Unclassifed Manufacturers – ADVANCED COMMUNICATIONS & SENSING

ADVANCED COMMUNICATIONS & SENSING
Index of Figures
Figure 1: RF64 Simplified Block Diagram ....................................... 5
Figure 2: RF64 Pin Diagram .......................................................... 6
Figure 3: RF64 Detailed Block Diagram ...................................... 12
Figure 4: Power Supply Breakdown............................................. 13
Figure 5: Frequency Synthesizer Description ............................... 14
Figure 6: LO Generator ................................................................ 14
Figure 7: Loop Filter ..................................................................... 16
Figure 8: Transmitter Architecture ............................................... 18
Figure 9: I(t), Q(t) Overview ......................................................... 18
Figure 10: PA Control................................................................... 21
Figure 11: Optimal Load Impedance Chart ................................... 21
Figure 12: Recommended PA Biasing and Output Matching ..... 22
Figure 13: Front-end Description ................................................. 22
Figure 14: Receiver Architecture ................................................. 23
Figure 15: FSK Receiver Setting ................................................. 23
Figure 16: OOK Receiver Setting ................................................ 23
Figure 17: Active Channel Filter Description................................ 24
Figure 18: Butterworth Filter's Actual BW .................................... 26
Figure 19: Polyphase Filter's Actual BW ...................................... 26
Figure 20: RSSI Dynamic Range ................................................. 27
Figure 21: RSSI IRQ Timings ...................................................... 28
Figure 22: OOK Demodulator Description .................................... 29
Figure 23: Floor Threshold Optimization...................................... 30
Figure 24: BitSync Description..................................................... 31
Figure 25: RF64‟s Data Processing Conceptual View .................. 34
Figure 26: SPI Interface Overview and uC Connections ............. 35
Figure 27: Write Register Sequence ............................................. 36
Figure 28: Read Register Sequence............................................ 37
Figure 29: Write Bytes Sequence (ex: 2 bytes) ........................... 37
Figure 30: Read Bytes Sequence (ex: 2 bytes) ........................... 38
Figure 31: FIFO and Shift Register (SR)...................................... 38
Figure 32: FIFO Threshold IRQ Source Behavior........................ 39
RF64
Figure 33: Sync Word Recognition ...............................................40
Figure 34: Continuous Mode Conceptual View.............................41
Figure 35: Tx Processing in Continuous Mode .............................41
Figure 36: Rx Processing in Continuous Mode.............................42
Figure 37: uC Connections in Continuous Mode ..........................43
Figure 38: Buffered Mode Conceptual View .................................44
Figure 39: Tx processing in Buffered Mode (FIFO size = 16,
Tx_start_irq_0=0) ..............................................................45
Figure 40: Rx Processing in Buffered Mode (FIFO size=16,
Fifo_fill_method=0)............................................................46
Figure 41: uC Connections in Buffered Mode ................................47
Figure 42: Packet Mode Conceptual View .....................................49
Figure 43: Fixed Length Packet Format........................................50
Figure 44: Variable Length Packet Format ....................................51
Figure 45: CRC Implementation ...................................................53
Figure 46: Manchester Encoding/Decoding ...................................54
Figure 47: Data Whitening .............................................................54
Figure 48: uC Connections in Packet Mode .................................55
Figure 49: Optimized Rx Cycle .....................................................67
Figure 50: Optimized Tx Cycle......................................................68
Figure 51: Tx Hop Cycle ...............................................................69
Figure 52: Rx Hop Cycle ...............................................................70
Figure 53: Rx => Tx => Rx Cycle ..................................................71
Figure 54: POR Timing Diagram...................................................72
Figure 55: Manual Reset Timing Diagram ....................................72
Figure 56: Reference Design Circuit Schematic ............................73
Figure 57: Reference Design„s Stackup .......................................74
Figure 58: Reference Design Layout (top view)............................74
Figure 59: Package Outline Drawing .............................................75
Figure 60: PCB Land Pattern .........................................................75
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