RF64 Datasheet, PDF (48/76 Pages) List of Unclassifed Manufacturers – ADVANCED COMMUNICATIONS & SENSING

RF64
ADVANCED COMMUNICATIONS & SENSING
 Write packet bytes into FIFO. Tx starts when the first byte is written (Tx_start_irq_0=1). We assume the FIFO is
being filled via SPI Data faster than being unfilled by SR (else use Tx_start_irq_0=0 ie Fifo_threshold to delay
Tx start)
 Wait for Tx_done interrupt (+1 bit period)
 Go to Sleep mode
Rx Mode:
 Program Rx/Stby interrupts: IRQ_0 mapped to /Fifoempty (Rx_stby_irq_0=10) and IRQ_1 mapped to
Fifo_threshold (Rx_stby_irq_1=01). Configure Fifo_thresh to an appropriate value (ex: to detect packet end if
its length is known)
 Go to Rx mode (note that Rx is not ready immediately, Cf section 7.3.1).
 Wait for Fifo_threshold interrupt (i.e. Sync word has been detected and FIFO filled up to the defined threshold).
 If it is packet end, go to Stby (SR‟s content is lost).
 Read packet bytes from FIFO until /Fifoempty goes low (or correct number of bytes is read).
 Go to Sleep mode.
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