RF64 Datasheet, PDF (14/76 Pages) List of Unclassifed Manufacturers – ADVANCED COMMUNICATIONS & SENSING

RF64
ADVANCED COMMUNICATIONS & SENSING
3.2.3. PLL Architecture
The crystal oscillator (XO) forms the reference oscillator of an Integer-N Phase Locked Loop (PLL), whose
operation is discussed in the following section. Figure 5 shows a block schematic of the RF64 PLL. Here the crystal
reference frequency and the software controlled dividers R, P and S determine the output frequency of the PLL.
(P )+ _i
÷75. i+1 S
XT_M
XO
XT_P
÷(R_i+1)
PFD
Fcomp
LF_M
Vtu e
n
LF_P
VCO_M
Figure 5: Frequency Synthesizer Description
LO
VCO_P
VR_VCO
The VCO tank inductors are connected on an external differential input. Similarly, the loop filter is also located
externally. However, there is an internal 8pF capacitance at VCO input that should be subtracted from the desired
loop filter capacitance.
The output signal of the VCO is used as the input to the local oscillator (LO) generator stage, illustrated in Figure 6.
The VCO frequency is subdivided and used in a series of up (down) conversions for transmission (reception).
÷8
LO
VCO Output
÷8
90°
90°
90°
LO1 Rx
I
LO2 Rx
Q
I
LO1 Tx
Q
I
LO2 Tx
Q
Receiver
LOs
Transmitter
LOs
Figure 6: LO Generator
3.2.4. PLL Tradeoffs
With an integer-N PLL architecture, the following criterion must be met to ensure correct operation:
 The comparison frequency, Fcomp, of the Phase Frequency Detector (PFD) input must remain higher than six
times the PLL bandwidth (PLLBW) to guarantee loop stability and to reject harmonics of the comparison
frequency Fcomp. This is expressed in the inequality:
PLLBW ≤ ^Fcomp
6
 However the PLLBW has to be sufficiently high to allow adequate PLL lock times
 Because the divider ration R determines Fcomp, it should be set close to 119, leading to Fcomp≈100 kHz
which will ensure suitable PLL stability and speed.
Page 14 of 76
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