RF64 Datasheet, PDF (47/76 Pages) List of Unclassifed Manufacturers – ADVANCED COMMUNICATIONS & SENSING

ADVANCED COMMUNICATIONS & SENSING
5.4.5. uC Connections
RF64
IRQ_0
IRQ_1
NSS_CONFIG
NSS_DATA
SCK
MOSI
MISO
uC
RF64
Figure 41: uC Connections in Buffered Mode
Note that depending upon the application, some uC connections may not be needed:
IRQ_0: if none of the relevant IRQ sources are used. In this case, leave floating.
IRQ_1: if none of the relevant IRQ sources are used. In this case, leave floating.
MISO: if no read register access is needed and the chip is used in Tx mode only. In this case, pull up to VDD
through a 100 kΩ resistor.
In addition, DATA pin (unused in buffered mode) should be pulled-up to VDD through a 100 kΩ resistor.
Please refer to Table 13 for the RF64‟s pin configuration.
5.4.6. Buffered Mode Example
 Configure all data processing related registers listed below appropriately. In this example we assume Sync
word recognition is on and Fifo_fill_method=0.
MCParam
IRQParam
RXParam
SYNCParam
Data_mode_x
Fifo_size
Fifo_thresh
Rx_stby_irq_0
Rx_stby_irq_1
Tx_irq_1
Fifo_fill_method
Fifo_fill
Tx_start_irq_0
Sync_size
Sync_tol
Sync_value
Tx
Rx
Description
X
X Defines data operation mode (=>Buffered)
X
X Defines FIFO size
X
X Defines FIFO threshold
X Defines IRQ_0 source in Rx & Stby modes
X Defines IRQ_1 source in Rx & Stby modes
X
Defines IRQ_1 source in Tx mode
X Defines FIFO filling method
X Controls FIFO filling status
X
Defines Tx start condition and IRQ_0 source
X Defines Sync word size
X Defines the error tolerance on Sync word detection
X Defines Sync word value
Table 22: Relevant Configuration Registers in Buffered Mode (data processing related only)
Tx Mode:
 Program Tx start condition and IRQs: Start Tx when FIFO is not empty (Tx_start_irq_0=1) and IRQ_1 mapped
to Tx_done (Tx_irq_1=1)
 Go to Tx mode (and wait for Tx to be ready, see Figure 50)
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