RF64 Datasheet, PDF (23/76 Pages) List of Unclassifed Manufacturers – ADVANCED COMMUNICATIONS & SENSING

ADVANCED COMMUNICATIONS & SENSING
3.4. Receiver Description
The RF64 is set to receive mode when MCParam_Chip_mode = 011.
First down-
conv e rsi on
Second down-
conversion
RSSI
LNA
LO2 Rx
OOK
demod
Bi t
synchronizer
FSK
demod
LO1 Rx
RF64
Control logic
-Pattern recognition
-FIFO handler
-SPI interface
-Packet handler
RF
IF1
Baseband, IF2 in OOK
Figure 14: Receiver Architecture
3.4.1. Architecture
The RF64 receiver employs a super-heterodyne architecture. Here, the first IF is 1/9^th of the RF frequency
(approximately 100MHz). The second down-conversion down-converts the I and Q signals to base band in the
case of the FSK receiver (Zero IF) and to a low-IF (IF2) for the OOK receiver.
LO2
Rx
S ec on d
down-conversion
First
d own-c on vers i on
0
IF2=0
in FSK
mode
IF1
≈100MHz
S ec on d
d own-c on vers ion
Figure 15: FSK Receiver Setting
Im ag e
frequ enc y
LO1 Rx
Channel
Frequ enc yl
First
down-c on vers ion
0
IF2<0 in
FSK mode
equal to fo
IF1
≈100MHz
LO2 Rx
Im ag e
frequ enc y
LO1 Rx
Channel
Freq u enc y
Figure 16: OOK Receiver Setting
After the second down-conversion stage, the received signal is channel-select filtered and amplified to a level
adequate for demodulation. Both FSK and OOK demodulation are available. Finally, an optional Bit Synchronizer
(BitSync) is provided, to be supply a synchronous clock and data stream to a companion uC in Continuous mode,
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