VS1053B Datasheet, PDF (66/79 Pages) List of Unclassifed Manufacturers – Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1053b preliminary
VS1053B
10. VS1053B REGISTERS
10.5 Serial Data Registers
Reg
0xC011
0xC012
Type
r
w
Reset
0
0
SDI registers, prefix SER
Abbrev[bits]
Description
DATA
Last received 2 bytes, big-endian
DREQ[0]
DREQ pin control
10.6 DAC Registers
Reg
0xC013
0xC014
0xC015
0xC016
Type
rw
rw
rw
rw
Reset
0
0
0
0
DAC registers, prefix DAC
Abbrev[bits]
Description
FCTLL
DAC frequency control, 16 LSbs
FCTLH
DAC frequency control 4MSbs, PLL control
LEFT
DAC left channel PCM value
RIGHT
DAC right channel PCM value
Every fourth clock cycle, an internal 26-bit counter is added to by (DAC FCTLH & 15) × 65536 +
DAC FCTLL. Whenever this counter overflows, values from DAC LEFT and DAC RIGHT are read and
a DAC interrupt is generated.
10.7 GPIO Registers
Reg
0xC017
0xC018
0xC019
Type
rw
r
rw
Reset
0
0
0
GPIO registers, prefix GPIO
Abbrev[bits]
Description
DDR[7:0]
IDATA[7:0]
Direction
Values read from the pins
ODATA[7:0]
Values set to the pins
GPIO DIR is used to set the direction of the GPIO pins. 1 means output. GPIO ODATA remembers its
values even if a GPIO DIR bit is set to input.
GPIO registers don’t generate interrupts.
Note that in VS1053b the VSDSP registers can be read and written through the SCI WRAMADDR and
SCI WRAM registers. You can thus use the GPIO pins quite conveniently.
Version 0.5, 2007-12-03
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