VS1053B Datasheet, PDF(39/79 Page) List of Unclassifed Manufacturers

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VS1053B Datasheet, PDF (39/79 Pages) List of Unclassifed Manufacturers – Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

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VLSI

Solution y

VS1053b preliminary

VS1053B

8. FUNCTIONAL DESCRIPTION

If SM TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 9.12.

SM STREAM activates VS1053bâs stream mode. In this mode, data should be sent with as even intervals

as possible and preferable in blocks of less than 512 bytes, and VS1053b makes every attempt to keep its

input buffer half full by changing its playback speed upto 5%. For best quality sound, the average speed

error should be within 0.5%, the bitrate should not exceed 160 kbit/s and VBR should not be used. For

details, see Application Notes for VS10XX. This mode only works with MP3 and WAV ï¬les.

SM DACT deï¬nes the active edge of data clock for SDI. When â0â, data is read at the rising edge, when

â1â, data is read at the falling edge.

When SM SDIORD is clear, bytes on SDI are sent MSb ï¬rst. By setting SM SDIORD, the user may

reverse the bit order for SDI, i.e. bit 0 is received ï¬rst and bit 7 last. Bytes are, however, still sent in the

default order. This register bit has no effect on the SCI bus.

Setting SM SDISHARE makes SCI and SDI share the same chip select, as explained in Chapter 7.2, if

also SM SDINEW is set.

Setting SM SDINEW will activate VS1002 native serial modes as described in Chapters 7.2.1 and 7.4.2.

Note, that this bit is set as a default when VS1053b is started up.

By activating SM ADPCM and SM RESET at the same time, the user will activate IMA ADPCM record-

ing mode (see section 9.8).

SM LINE IN is used to select the left-channel input for ADPCM recording. If â0â, differential micro-

phone input pins MICP and MICN are used; if â1â, line-level MICP/LINEIN1 pin is used.

SM CLK RANGE activates a clock divider in the XTAL input. When SM CLK RANGE is set, the

clock is divided by 2 at the input. From the chipâs point of view e.g. 24 MHz becomes 12 MHz.

SM CLK RANGE should be set as soon as possible after a chip reset.

Version 0.5, 2007-12-03

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