VS1053B Datasheet, PDF (14/79 Pages) List of Unclassifed Manufacturers – Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1053b preliminary
VS1053B
5. PACKAGES AND PIN DESCRIPTIONS
Pad Name
LQFP Pin
Pin Type
Function
MICP / LINE1
1
MICN
2
XRESET
3
DGND0
4
CVDD0
5
IOVDD0
6
CVDD1
7
DREQ
8
GPIO2 / DCLK¹
9
GPIO3 / SDATA¹
10
GPIO6 / I2S SCLK³ 11
GPIO7 / I2S SDATA³ 12
AI
AI
DI
DGND
CPWR
IOPWR
CPWR
DO
DIO
DIO
DIO
DIO
Positive differential mic input, self-biasing / Line-in 1
Negative differential mic input, self-biasing
Active low asynchronous reset, schmitt-trigger input
Core & I/O ground
Core power supply
I/O power supply
Core power supply
Data request, input bus
General purpose IO 2 / serial input data bus clock
General purpose IO 3 / serial data input
General purpose IO 6 / I2S SCLK
General purpose IO 7 / I2S SDATA
XDCS / BSYNC¹
IOVDD1
VCO
DGND1
XTALO
XTALI
IOVDD2
DGND2
DGND3
DGND4
XCS
CVDD2
13 DI
Data chip select / byte sync
14 IOPWR I/O power supply
15 DO
For testing only (Clock VCO output)
16 DGND Core & I/O ground
17 AO
Crystal output
18 AI
Crystal input
19 IOPWR I/O power supply
20 DGND Core & I/O ground
21 DGND Core & I/O ground
22 DGND Core & I/O ground
23 DI
Chip select input (active low)
24 CPWR Core power supply
GPIO5 / I2S MCLK³ 25
RX
26
TX
27
SCLK
28
SI
29
SO
30
CVDD3
31
XTEST
32
GPIO0
33
GPIO1
34
GND
35
GPIO4 / I2S LROUT³ 36
DIO
DI
DO
DI
DI
DO3
CPWR
DI
DIO
DIO
DGND
DIO
General purpose IO 5 / I2S MCLK
UART receive, connect to IOVDD if not used
UART transmit
Clock for serial bus
Serial input
Serial output
Core power supply
Reserved for test, connect to IOVDD
Gen. purp. IO 0 (SPIBOOT), use 100 kΩ pull-down resistor²
General purpose IO 1
I/O Ground
General purpose IO 4 / I2S LROUT
AGND0
AVDD0
RIGHT
AGND1
AGND2
GBUF
AVDD1
RCAP
AVDD2
LEFT
AGND3
LINE2
37 APWR Analog ground, low-noise reference
38 APWR Analog power supply
39 AO
Right channel output
40 APWR Analog ground
41 APWR Analog ground
42 AO
Common buffer for headphones, do NOT connect to ground!
43 APWR Analog power supply
44 AIO
Filtering capacitance for reference
45 APWR Analog power supply
46 AO
Left channel output
47 APWR Analog ground
48 AI
Line-in 2 (right channel)
1 _{First pin function is active in New Mode, latter in Compatibility Mode.}
2 _{Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.9 for details.}
3 _{If I2S CF ENA is ’0’ the pins are used for GPIO. See Chapter 10.13 for details.}
Version 0.5, 2007-12-03
14