VS1053B Datasheet, PDF (48/79 Pages) List of Unclassifed Manufacturers – Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1053b preliminary
VS1053B
9. OPERATION
9 Operation
9.1 Clocking
VS1053b operates on a single, nominally 12.288 MHz fundamental frequency master clock. This clock
can be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface
(pins XTALI and XTALO). This clock is used by the analog parts and determines the highest available
samplerate. With 12.288 MHz clock all samplerates upto 48000 Hz are available.
VS1053b can also use 24..26 MHz clocks when SM CLK RANGE in the SCI MODE register is set to
1. The system clock is then divided by 2 at the clock input and the chip gets a 12..13 MHz input clock.
9.2 Hardware Reset
When the XRESET -signal is driven low, VS1053b is reset and all the control registers and internal
states are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode
doubles as a full-powerdown mode, where both digital and analog parts of VS1053b are in minimum
power consumption stage, and where clocks are stopped. Also XTALO is grounded.
When XRESET is asseted, all output pins go to their default states. All input pins will go to high-
impedance state (to input state), except SO, which is still controlled by the XCS.
After a hardware reset (or at power-up) DREQ will stay down for around 22000 clock cycles, which
means an approximate 1.8 ms delay if VS1053b is run at 12.288 MHz. After this the user should set
such basic software registers as SCI MODE, SCI BASS, SCI CLOCKF, and SCI VOL before starting
decoding. See section 8.7 for details.
If the input clock is 24..26 MHz, SM CLK RANGE should be set as soon as possible after a chip reset
without waiting for DREQ.
Internal clock can be multiplied with a PLL. Supported multipliers through the SCI CLOCKF register
are 1.0 × . . . 5.0× the input clock. Reset value for Internal Clock Multiplier is 1.0×. If typical values
are wanted, the Internal Clock Multiplier needs to be set to 3.5× after reset. Wait until DREQ rises, then
write value 0x9800 to SCI CLOCKF (register 3). See section 8.7.4 for details.
9.3 Software Reset
In some cases the decoder software has to be reset. This is done by activating bit SM RESET in register
SCI MODE (Chapter 8.7.1). Then wait for at least 2 µs, then look at DREQ. DREQ will stay down for
about 22000 clock cycles, which means an approximate 1.8 ms delay if VS1053b is run at 12.288 MHz.
After DREQ is up, you may continue playback as usual.
As opposed to all earlier VS10XX chips, it is not recommended to do a software reset between songs.
This way the user may be sure that even files with low samplerates or bitrates are played right to their
end.
Version 0.5, 2007-12-03
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