VS1053B Datasheet, PDF (22/79 Pages) List of Unclassifed Manufacturers – Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1053b preliminary
VS1053B
7. SPI BUSES
After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the
WRITE sequence.
After the last bit has been sent, DREQ is driven low for the duration of the register update, marked
“execution” in the figure. The time varies depending on the register and its contents (see table in Chap-
ter 8.7 for details). If the maximum time is longer than what it takes from the microcontroller to feed
the next SCI command or SDI byte, status of DREQ must be checked before finishing the next SCI/SDI
operation.
7.5.4 SCI Multiple Write
XCS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 29 30 31
3 2 1 0 15 14
000000100000
10
X
instruction (write)
address
data out 1
00 00 00 00 00 00 00 00 00
00
32 33 m−2m−1
15 14
10
X
data out 2 d.out n
00
0 0X
DREQ
execution
execution
Figure 8: SCI Multiple Word Write
VS1053b allows for the user to send multiple words to the same SCI register, which allows fast SCI
uploads, shown in Figure 8. The main difference to a single write is that instead of bringing XCS up
after sending the last bit of a data word, the next data word is sent immediately. After the last data word,
XCS is driven high as with a single word write.
After the last bit of a word has been sent, DREQ is driven low for the duration of the register update,
marked “execution” in the figure. The time varies depending on the register and its contents (see table
in Chapter 8.7 for details). If the maximum time is longer than what it takes from the microcontroller
to feed the next SCI command or SDI byte, status of DREQ must be checked before finishing the next
SCI/SDI operation.
Version 0.5, 2007-12-03
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