VS1053B Datasheet, PDF (37/79 Pages) List of Unclassifed Manufacturers – Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1053b preliminary
VS1053B
8. FUNCTIONAL DESCRIPTION
8.7 SCI Registers
VS1053b sets DREQ low when it detects an SCI operation (this delay is 16 to 40 CLKI cycles depending
on whether an interrupt service routine is active) and restores it when it has processed the operation. The
duration depends on the operation. If DREQ is low when an SCI operation is performed, it also stays
low after SCI operation processing.
If DREQ is high before a SCI operation, do not start a new SCI/SDI operation before DREQ is high
again. If DREQ is low before a SCI operation because the SDI can not accept more data, make certain
there is enough time to complete the operation before sending another.
SCI registers, prefix SCI
Reg Type Reset
Time¹ Abbrev[bits]
Description
0x0 rw 0x4800
80 CLKI⁴ MODE
Mode control
0x1 rw 0x000C³
80 CLKI STATUS
Status of VS1053b
0x2 rw 0
80 CLKI BASS
Built-in bass/treble control
0x3 rw 0
1200 XTALI⁵ CLOCKF
Clock freq + multiplier
0x4 rw 0
100 CLKI DECODE TIME Decode time in seconds
0x5 rw 0
450 CLKI² AUDATA
Misc. audio data
0x6 rw 0
100 CLKI WRAM
RAM write/read
0x7 rw 0
100 CLKI WRAMADDR Base address for RAM write/read
0x8 r 0
80 CLKI HDAT0
Stream header data 0
0x9 r 0
80 CLKI HDAT1
Stream header data 1
0xA rw 0
210 CLKI² AIADDR
Start address of application
0xB rw 0
80 CLKI VOL
Volume control
0xC rw 0
80 CLKI² AICTRL0
Application control register 0
0xD rw 0
80 CLKI² AICTRL1
Application control register 1
0xE rw 0
80 CLKI² AICTRL2
Application control register 2
0xF rw 0
80 CLKI² AICTRL3
Application control register 3
1 _{This is the worst-case time that DREQ stays low after writing to this register. The user may choose to}
skip the DREQ check for those register writes that take less than 100 clock cycles to execute and use a
fixed delay instead.
2 _{In addition, the cycles spent in the user application routine must be counted.}
3 _{Firmware changes the value of this register immediately to 0x48 (analog enabled), and after a short}
while to 0x40 (analog drivers enabled).
4 _{When mode register write specifies a software reset the worst-case time is 22000 XTALI cycles.}
5 _{Writing to CLOCKF register may force internal clock to run at 1.0 × XTALI for a while. Thus it is not}
a good idea to send SCI or SDI bits while this register update is in progress.
Reads from all SCI registers complete in under 100 CLKI cycles, except a read from AIADDR in 200
cycles. In addition the cycles spent in the user application routine must be counted to the read time of
AIADDR, AUDATA, and AICTRL0..3.
Version 0.5, 2007-12-03
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