VS1053B Datasheet, PDF (18/79 Pages) List of Unclassifed Manufacturers – Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1053b preliminary
VS1053B
7. SPI BUSES
7 SPI Buses
7.1 General
The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1053b’s
Serial Data Interface SDI (Chapters 7.4 and 8.5) and Serial Control Interface SCI (Chapters 7.5 and 8.6).
7.2 SPI Bus Pin Descriptions
7.2.1 VS1002 Native Modes (New Mode)
These modes are active on VS1053b when SM SDINEW is set to 1 (default at startup). DCLK and
SDATA are not used for data transfer and they can be used as general-purpose I/O pins (GPIO2 and
GPIO3). BSYNC function changes to data interface chip select (XDCS).
SDI Pin SCI Pin
XDCS XCS
SCK
SI
-
SO
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. If SM SDISHARE is 1, pin
XDCS is not used, but the signal is generated internally by inverting
XCS.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. If a chip select is active, SI is sampled on the rising CLK edge.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
7.2.2 VS1001 Compatibility Mode (deprecated)
This mode is active when SM SDINEW is set to 0. In this mode, DCLK, SDATA and BSYNC are active.
SDI Pin
-
BSYNC
DCLK
SDATA
-
SCI Pin
XCS
-
SCK
SI
SO
Description
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state.
SDI data is synchronized with a rising edge of BSYNC.
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written.
Serial input. SI is sampled on the rising SCK edge, if XCS is low.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
Version 0.5, 2007-12-03
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