VS1053B Datasheet, PDF (19/79 Pages) List of Unclassifed Manufacturers – Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1053b preliminary
VS1053B
7. SPI BUSES
7.3 Data Request Pin DREQ
The DREQ pin/signal is used to signal if VS1053b’s 2048-byte FIFO is capable of receiving data. If
DREQ is high, VS1053b can take at least 32 bytes of SDI data or one SCI command. DREQ is turned
low when the stream buffer is too full and for the duration of a SCI command.
Because of the 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time without
checking the status of DREQ, making controlling VS1053b easier for low-speed microcontrollers.
Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should
only be used to decide whether to send more bytes. It does not need to abort a transmission that has
already started.
Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1053b DREQ is also
used to tell the status of SCI.
There are cases when you still want to send SCI commands when DREQ is low. Because DREQ is
shared between SDI and SCI, you can not determine if a SCI command has been executed if SDI is not
ready to receive. In this case you need a long enough delay after every SCI command to make certain
none of them is missed. The SCI Registers table in section 8.7 gives the worst-case handling time for
each SCI register write.
7.4 Serial Protocol for Serial Data Interface (SDI)
7.4.1 General
The serial data interface operates in slave mode so DCLK signal must be generated by an external circuit.
Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.7).
VS1053b assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or
LSb first, depending of contents of SCI MODE (Chapter 8.7.1).
The firmware is able to accept the maximum bitrate the SDI supports.
7.4.2 SDI in VS1002 Native Modes (New Mode)
In VS1002 native modes (SM NEWMODE is 1), byte synchronization is achieved by XDCS. The state of
XDCS may not change while a data byte transfer is in progress. To always maintain data synchronization
even if there may be glitches in the boards using VS1053b, it is recommended to turn XDCS every now
and then, for instance once after every disk data block, just to make sure the host and VS1053b are in
sync.
If SM SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.
For new designs, using VS1002 native modes are recommended.
Version 0.5, 2007-12-03
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