SLFLD25-128J Datasheet, PDF (4/21 Pages) List of Unclassifed Manufacturers – 128 MB to 8 GB 2.5-Inch IDE Flash Drives

SLFLD25-xxxJ(I)
IDE FLASH DRIVE
Signal Description
Signal Name
-DASP
D15-D00
-IOWR
-IORD
INTRQ
A2-A0
-CS1, -CS2
-CSEL
-IOIS16
-PDIAG
-DREQ
-DACK
-IORDY
-RESET
VCC
GND
Key
Dir
Pin
Description
I/O
39
This input/output is the Disk Active/Slave Present signal in the Master/
Slave handshake protocol.
I/O 18, 16, 14, 12, All Task File operations occur in byte mode on the low order bus D00-D07
10, 8, 6, 4, 3, while all data transfers are 16 bit using D00-D15.
5, 7, 9, 11, 13,
15, 17
I
23
The I/O Write strobe pulse is used to clock I/O data on the drive Data
bus into the Drive controller registers when the Drive is configured to
use the I/O interface. The clocking will occur on the negative to
positive edge of the signal (trailing edge).
I
25
This is an I/O Read strobe generated by the host. This signal gates I/O
data onto the bus from the Drive.
O
31
Signal is the active high Interrupt Request to the host.
I 35, 33, 36 A[2:0] are used to select the one of eight registers in the Task File.
I
37, 38 -CS1 is the chip select for the task file registers while -CS2 is used to select
the Alternate Status Register and the Device Control Register.
I
28
This internally pulled up signal is used to configure this device as a Master
or a Slave. When the pin is grounded, this device is configured as a Master.
When the pin is open, this device is configured as a Slave
O
32
Not used.
I/O
34
This input/output is the Pass Diagnostic signal in the Master/Slave
handshake protocol.
O
21
Not used.
I
29
Not used.
O
27
Not used, and pulled up to VCC through a 4.7K ohm resistor.
I
1
This input pin is the active low hardware reset from the host.
—
41, 42 Power.
— 2, 19, 22, 24, Ground.
26, 30, 40, 43
—
20
This pin is keyed to ensure cable is connected with the proper orientation.
Document Part Number 61000-02817-109 March 2005 Page 4