SLFLD25-128J Datasheet, PDF (15/21 Pages) List of Unclassifed Manufacturers – 128 MB to 8 GB 2.5-Inch IDE Flash Drives

SLFLD25-xxxJ(I)
IDE FLASH DRIVE
Device Control Register
This write only register is used for controlling the interrupt
request and issuing an ATA soft reset to the drive.
bit7
x
bit6
x
bit5
x
bit4
x
bit3
1
bit2
SRST
bit1
nIEN
bit0
0
bit Name
7-4 x
31
2 SRST (Software ReSeT)
1 nIEN (Interrupt ENable)
00
Function
Don’t care.
This bit is set to “1”.
This bit is set to “1” in order to force the drive to perform an AT disk control
soft reset operation.
When set to “0”, it enables interrupts to the host (using the -IREQ tri-state
pin). When inactive (set to “1”) or drive is not selected, it disables all pending
interrupts (-IREQ in high-Z). This bit is ignored in memory mode.
This bit is set to “0”.
Drive Address Register
This read only register is used for confirming the drive’s
status. This register is provided for compatibility with the AT
disk drive interface and it is not recommended that this
register be mapped into the host’s I/O space because of
potential conflicts on bit 7.
bit7
High-Z
bit6
nWTG
bit5
nHS3
bit4
nHS2
bit3
nHS1
bit2
nHS0
bit1
nDS1
bit0
nDS0
bit Name
7x
6 nWTG (WriTing Gate)
5-2 nHS3-0 (Head Select 3-0)
1 nDS1 (Drive Select 1)
0 nDS0 (Drive Select 0)
Function
This bit is unused.
This bit is unused.
These bits are the negative value of the Head Select bits (bit 3 to 0) in the
Drive/Head register
When set to “0”, drive 1 is active and selected.
When set to “0”, drive 0 is active and selected.
Document Part Number 61000-02817-109 March 2005 Page 15