SLFLD25-128J Datasheet, PDF (13/21 Pages) List of Unclassifed Manufacturers – 128 MB to 8 GB 2.5-Inch IDE Flash Drives

SLFLD25-xxxJ(I)
IDE FLASH DRIVE
Drive/Head Register
This register select the device address translation (CHS or
LBA) and provides head address (CHS) or high order
address bits 27:24 for LBA.
bit7
1
bit6
LBA
bit5
1
bit4
DRV
bit3
bit2
bit1
Head No. or LBA bits 27:24
bit0
bit Name
71
6 LBA
51
4 DRV (DRiVe select)
3-0 Head Number (HS3-HS0)
Function
This bit is set to “1”.
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block
Address (LBA) mode. When LBA=0, CHS mode is selected. When LBA=1, LBA
mode is selected. In LBA mode, the Logical Block Address is interrupted as
follows:
LBA07-LBA00: Sector Number Register D7-D0
LBA15-LBA08: Cylinder Low Register D7-D0
LBA23-LBA16: Cylinder High Register D7-D0
LBA27-LBA24: Drive/Head Register bits HS3-HS0
This bit is set to “1”.
This bit is used for selecting the Master (drive 0) and Slave (drive 1) in
Master/Slave organization. The drive is set to be drive 0 or 1 by using DRV# of
the Socket and Copy register.
These bits are used for selecting the Head number. Bit 3 is MSB. In LBA mode,
these bits represent the LBA address 27:24.
Document Part Number 61000-02817-109 March 2005 Page 13