SED1520D0A Datasheet, PDF (9/52 Pages) List of Unclassifed Manufacturers – DOT MATRIX LCD DRIVER

2.0 Block Diagrams
2.3 – 2.3.1.3
2.3 DESCRIPTION OF CIRCUIT BLOCKS
2.3.1 MPU Interface
2.3.1.1 Selection of Interface Type
The SED1520 Series uses 8 bits of bi-directional data bus (D0–D7) to transfer data. The reset pin
is capable of selecting MPU interface; setting the polarity of RES to either “H” or “L” can provide
direct interface of the SED1520 with a 68 or 80 family MPU (see Table 1 below).
With CS at high level, the SED1520 is independent from the MPU bus and stays in standby mode.
In this mode, however, the reset signal is input independently of the internal status.
Table 1
Polarity of RES
“L” active
“H” active
Type
68 MPU
80 MPU
A0
E
R/W
CS
↑
↑
↑
↑
↑
RD
WR
↑
D0–D7
↑
↑
2.3.1.2 Identification of Data Bus Signals
The SED1520 uses a combination of A0, E, R/W, (RD, WR) to identify a data bus signal.
Table 2
Common
A0
1
1
0
0
68 MPU
R/W
1
0
1
0
80 MPU
RD
WR
0
1
1
0
0
1
1
0
Function
Read display data
Write display data
Read status
Write to internal register (command)
2.3.1.3 Access to Display Data RAM and Internal Register
In order to make matching of operating frequencies between the MPU and the display data RAM
or internal register, the SED1520 performs a sort of LSI–LSI pipelining via the bus holder attached
to the internal data bus.
Consider the case where the MPU reads the content of the display data RAM. In the first data read
cycle (dummy), the data is stored on the bus holder. In the next data read cycle, the data is read
from the bus holder to the system bus.
Also, consider the case where the MPU writes data to the display data RAM. In the first data write
cycle, the data is held on the bus holder. The data is written to the display data RAM before the
next data write cycle begins.
371-1.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: [phone] • Fax: [phone]