SED1520D0A Datasheet, PDF (21/52 Pages) List of Unclassifed Manufacturers – DOT MATRIX LCD DRIVER

3.0 Pin Configuration
3.2.3 – 3.2.3
CS
Chip Select input signal which is normally obtained by decoding an address bus sig-
nal. Effective with “L” active and a chip operating with external clocks. For a chip con-
taining an oscillator, CS works as an oscillation amplifier input pin to which an
oscillation resistor (Rf) is connected. In this case, RD, WR and E must be a signal
ANDed with CS.
E(RD)
Chip interfaced with 68 family MPU:
Enable Clock signal input for the 68 family MPU.
Chip interfaced with 80 family MPU:
“L” Active input pin to which the 80 family MPU RD signal is connected.
With this signal held at “L”, the SED1520 data bus works as output.
R/W (WR)
Chip interface with 68 family MPU:
Read/Write control signal input pin.
R/W = “H” : Read
R/W = “L” : Write
Chip interfaced with 80 family MPU:
“L” Active input pin to which the 80 family WR is connected. The signal
on the data bus is fetched by the leading edge of WR.
3.2.3 LCD Drive Circuit Signals
CL
Input signal effective with a chip using external clocks. This display data latch signal
increments the line counter (at the trailing edge) or the common counter (at the lead-
ing edge). CL is connected to CL2 of the common driver. For a chip containing an
oscillator, this pin works as the oscillation amplifier output pin to which an oscillation
resistor (Rf) is connected.
FR
LCD AC signal I/O pin. Connected to pin M of the common driver.
I/O selection:
Chip containing commons M/S = 1 : Output
M/S = 0 : Input
Chip containing segments alone
: Input
371-1.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: [phone] • Fax: [phone]