SED1520D0A Datasheet, PDF (10/52 Pages) List of Unclassifed Manufacturers – DOT MATRIX LCD DRIVER

2.3.1.4 – 2.3.1.5
2.0 Block Diagrams
Therefore, MPU’s access to the SED1520 is affected not by display data RAM access time (tACC,
tDS) but by cycle time (tCYC). This leads to faster transfer of data to and from the MPU. If the cycle
time requirement is not met, the MPU has only to execute the NOP instruction and this is appar-
ently equivalent to execution of a waiting operation. However, there is a restriction on the read
sequence of the display data RAM; when an address is set, its data is output not to the first read
instruction (immediately following the address setting operation) but to the second read instruction.
Thus, one dummy read cycle is necessary after an address set or write cycle. This relation is
shown in Figures 2.3.1.4 and 2.3.1.5.
2.3.1.4 Write Timing Diagram
MPU
Internal
Timing
WR
DATA
Bus
Holder
WR
N
N+1
N+2
N+3
N
N+1
N+2
N+3
2.3.1.5 Read Timing Diagram
WR
MPU
RD
DATA
WR
Internal
Timing
RD
Column
Address
Bus
Holder
N
Address Set
at N
N
Dummy Read
n
Data Read
at N
n+1
Data Read
at N+1
N
N
N+1
n
N+2
n+1
n+2
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