SED1520D0A Datasheet, PDF (12/52 Pages) List of Unclassifed Manufacturers – DOT MATRIX LCD DRIVER

2.3.7 – 2.3.8
2.0 Block Diagrams
2.3.7 Common Timing Generator
This circuit generates common timing and frame (FR) signals from the basic clock (CL). The Se-
lect Duty command selects a duty of 1/16 or 1/32. The 1/32 duty is achieved by a two-chip (master
and slave) configuration (common multi-chip system).
2.3.7.1 Common Timing Diagram
FR
(Master
Output)
Master
Common
Slave
Common
012
14 15
16 17
01
30 31
15
16 17
31
2.3.8 Display Data Latch Circuit
The display data latch circuit temporarily stores the data which will be output from the display
data RAM to the LCD driver circuit at one-common intervals. The display ON/OFF and Static
Driver ON/OFF commands control the latched data so that the data in the display data RAM
remains unchanged.
12 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: [phone] • Fax: [phone]