SED1520D0A Datasheet, PDF (22/52 Pages) List of Unclassifed Manufacturers – DOT MATRIX LCD DRIVER

3.2.3.1 – 3.2.3.2
3.0 Pin Configuration
SEG0– LCD column (segment) driving output. One of the VDD, V2, V3 and V5 levels is
SEG79 selected by a combination of the content of display RAM and the FR signal.
3.2.3.1 LCD Column (Segment) Driving Output Timing
FR
DATA
Output Level
1
0
1010
V_DD V₂ V₅ V₃
COM0– LCD common (row) driving output. One of the VDD, V1, V4 and V5 levels is
COM15 selected by a combination of the output of the common counter and the FR
(COM31– signal. The common (row) scanning order for the slave LSI is reverse to that for
COM16) the master LSI.
3.2.3.2 LCD common (row) driving output
FR
Counter Output
Output Level
1
0
1010
V_S V₁ V_DD V₄
M/S
Input signal which selects the master or slave LSI. Connected to VDD or VSS.
(SEG79)
M/S = VDD: Master
M/S = VSS : Slave
M/S selection changes the function of pins FR, COM0–COM15, OSC1 (CS) and
OSC2 (CL):
M/S
FR
VDD
Output
VSS
Input
COM output
COM0–COM15
COM31–COM16
OSC1
Input
NC
OSC2
Output
Input
The common scanning order for the slave driver is reverse to that for master.
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