SED1520D0A Datasheet, PDF (14/52 Pages) List of Unclassifed Manufacturers – DOT MATRIX LCD DRIVER

2.3.9 – 2.3.11
2.0 Block Diagrams
2.3.9 LCD Driver Circuit
This circuit generates 80 sets of multiplexer that generate quartet levels for LCD driving. Display
data in the display data latch, common timing generator output and FR signal are combined to out-
put an LCD driving waveform.
2.3.10 Display Timing Generator
This circuit generates an internal display timing signal from the basic clock (CL) and frame signal (FR).
The frame signal FR makes the LCD driver circuit generate a dual frame AC driving waveform
(type B) to drive LCD, while making both the line counter and common timing generator synchro-
nized to the FR signal output LSI (dedicated common driver or the SED1520 master LSI). To
achieve these functions, the FR signal must be a clock with a duty of 50% which is synchronized
to the frame period.
The clock CL is a clock used to operate the line counter. For a system in which both the SED1520
and SED1521F coexist, they should be of LSI types having the same clock frequency to be applied
to pin CL.
2.3.11 Oscillation Circuit
This circuit is a low-power CR oscillator which uses an oscillation resistor Rf alone to adjust the
oscillation frequency. It generates display timing signals. The SED1520 is available in two LSI
types if classified by oscillation: one LSI type contains an oscillation circuit and the other uses an
externally provided clock.
The oscillation resistor Rf is connected as shown below. Where an LSI containing an oscillation
circuit is operated with an external clock, it is necessary to input the clock with the same phase as
OSC2 of the master LSI to OSC2 of the slave LSI.
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